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| author | H.J. Lu <hjl.tools@gmail.com> | 2017-05-23 20:22:13 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2017-05-24 06:35:25 -0700 |
| commit | 42419536fd1effe9a05fa4efa92742b52e2ffae8 (patch) | |
| tree | f33e4d3b507a9978e481064886e1cd56284df13a /sysdeps/x86/cacheinfo.c | |
| parent | 9c450f6f6f0e2089b780d0510ae6153740fc7d1d (diff) | |
| download | glibc-hjl/cacheinfo/master.tar.xz glibc-hjl/cacheinfo/master.zip | |
x86: Add cache info to cpu_featureshjl/cacheinfo/master
This patch adds cache info to cpu_features to support tunables for both
cache info as well as CPU features in a single x86 namespace. Since
init_cacheinfo is in libc.so and cpu_features is in ld.so, cache info
and CPU features must be in a place for tunables.
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Use data_size,
shared_size and non_temporal_threshold from cpu_features if
they aren't zero.
* sysdeps/x86/cpu-features.h (cache_info): New.
(cpu_features): Add cache.
Diffstat (limited to 'sysdeps/x86/cacheinfo.c')
| -rw-r--r-- | sysdeps/x86/cacheinfo.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 12ffeef5b5..321fbb6310 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -745,6 +745,9 @@ intel_bug_no_cache_info: #endif } + if (cpu_features->cache.data_size != 0) + data = cpu_features->cache.data_size; + if (data > 0) { __x86_raw_data_cache_size_half = data / 2; @@ -755,6 +758,9 @@ intel_bug_no_cache_info: __x86_data_cache_size = data; } + if (cpu_features->cache.shared_size != 0) + shared = cpu_features->cache.shared_size; + if (shared > 0) { __x86_raw_shared_cache_size_half = shared / 2; @@ -768,7 +774,10 @@ intel_bug_no_cache_info: /* The large memcpy micro benchmark in glibc shows that 6 times of shared cache size is the approximate value above which non-temporal store becomes faster. */ - __x86_shared_non_temporal_threshold = __x86_shared_cache_size * 6; + __x86_shared_non_temporal_threshold + = (cpu_features->cache.non_temporal_threshold != 0 + ? cpu_features->cache.non_temporal_threshold + : __x86_shared_cache_size * 6); } #endif |