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2025-04-12x86: Detect Intel Diamond Rapidsrelease/2.40/masterH.J. Lu1-0/+12
2025-04-12x86: Handle unknown Intel processor with default tuningSunil K Pandey1-143/+143
2025-04-12x86: Add ARL/PTL/CWF model detection supportSunil K Pandey1-0/+10
2025-04-12x86: Optimize xstate size calculationSunil K Pandey2-56/+24
2025-04-12x86: Use `Avoid_Non_Temporal_Memset` to control non-temporal pathNoah Goldstein2-8/+23
2025-03-31x86: Link tst-gnu2-tls2-x86-noxsave{,c,xsavec} with libpthreadFlorian Weimer1-0/+3
2025-03-29x86: Use separate variable for TLSDESC XSAVE/XSAVEC state size (bug 32810)Florian Weimer10-8/+41
2025-03-29x86: Skip XSAVE state size reset if ISA level requires XSAVEFlorian Weimer1-0/+5
2025-03-18x86_64: Add atanh with FMASunil K Pandey5-0/+51
2025-03-18x86_64: Add sinh with FMASunil K Pandey5-0/+58
2025-03-18x86_64: Add tanh with FMASunil K Pandey4-0/+49
2025-03-12nptl: clear the whole rseq area before registrationMichael Jeanson2-6/+6
2025-02-28math: Improve layout of exp/exp10 dataWilco Dijkstra1-2/+4
2025-02-28AArch64: Use prefer_sve_ifuncs for SVE memsetWilco Dijkstra1-1/+1
2025-02-28AArch64: Add SVE memsetWilco Dijkstra4-0/+129
2025-02-28math: Improve layout of expf dataWilco Dijkstra1-1/+1
2025-02-28AArch64: Remove zva_128 from memsetWilco Dijkstra1-24/+1
2025-02-28AArch64: Optimize memsetWilco Dijkstra1-111/+84
2025-02-28AArch64: Improve generic strlenWilco Dijkstra1-12/+27
2025-02-27Revert "AArch64: Add vector logp1 alias for log1p"Wilco Dijkstra10-42/+1
2025-02-27AArch64: Improve codegen for SVE powfYat Long Poon1-58/+59
2025-02-27AArch64: Improve codegen for SVE powYat Long Poon1-103/+142
2025-02-27AArch64: Improve codegen for SVE erfcfYat Long Poon1-6/+6
2025-02-27Aarch64: Improve codegen in SVE exp and users, and update expf_inlineLuna Lamb5-49/+59
2025-02-27Aarch64: Improve codegen in SVE asinhLuna Lamb1-34/+77
2025-02-27AArch64: Improve codegen in SVE expm1f and usersLuna Lamb4-45/+44
2025-02-27AArch64: Improve codegen for SVE log1pf usersYat Long Poon5-122/+95
2025-02-27AArch64: Improve codegen for SVE logsYat Long Poon4-47/+114
2025-02-27AArch64: Improve codegen in SVE tansLuna Lamb2-41/+68
2025-02-27AArch64: Improve codegen in AdvSIMD asinhLuna Lamb1-55/+119
2025-02-27AArch64: Improve codegen of AdvSIMD expf familyJoana Cruz5-118/+127
2025-02-27AArch64: Improve codegen of AdvSIMD atan(2)(f)Joana Cruz3-68/+160
2025-02-27AArch64: Improve codegen of AdvSIMD logf function familyJoana Cruz3-40/+66
2025-02-27AArch64: Improve codegen in users of ADVSIMD log1p helperPierre Blanchard4-127/+93
2025-02-27AArch64: Improve codegen in AdvSIMD logsPierre Blanchard3-106/+140
2025-02-27AArch64: Improve codegen in AdvSIMD powPierre Blanchard1-53/+62
2025-02-27AArch64: Remove SVE erf and erfc tablesJoe Ramsay16-2691/+50
2025-02-27AArch64: Small optimisation in AdvSIMD erf and erfcJoe Ramsay2-15/+23
2025-02-27AArch64: Simplify rounding-multiply pattern in several AdvSIMD routinesJoe Ramsay5-38/+30
2025-02-27AArch64: Improve codegen in users of ADVSIMD expm1f helperJoe Ramsay4-91/+58
2025-02-27AArch64: Improve codegen in users of AdvSIMD log1pf helperJoe Ramsay5-139/+146
2025-02-27AArch64: Improve codegen in SVE F32 logsJoe Ramsay3-47/+69
2025-02-27AArch64: Improve codegen in SVE expf & related routinesJoe Ramsay5-148/+136
2025-02-27AArch64: Add vector logp1 alias for log1pJoe Ramsay10-1/+42
2025-02-27aarch64: Avoid redundant MOVs in AdvSIMD F32 logsJoe Ramsay3-45/+72
2025-02-25math: Add optimization barrier to ensure a1 + u.d is not reused [BZ #30664]John David Anglin1-0/+3
2025-02-13assert: Add test for CVE-2025-0395Siddhesh Poyarekar2-0/+93
2025-02-02nptl: Correct stack size attribute when stack grows up [BZ #32574]John David Anglin1-2/+2
2025-01-25stdlib: Test using setenv with updated environ [BZ #32588]H.J. Lu2-0/+37
2025-01-24malloc: obscure calloc use in tst-callocSam James1-4/+8
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-01 03:36:51 +0000