From cd7ce12a027656ad3cda774454088de5a2c7fbfa Mon Sep 17 00:00:00 2001 From: "Paul A. Clarke" Date: Fri, 12 Jul 2019 20:13:58 -0500 Subject: [powerpc] fe{en,dis}ableexcept optimize bit translations The exceptions passed to fe{en,dis}ableexcept() are defined in the ABI as a bitmask, a combination of FE_INVALID, FE_OVERFLOW, etc. Within the functions, these bits must be translated to/from the corresponding enable bits in the Floating Point Status Control Register (FPSCR). This translation is currently done bit-by-bit. The compiler generates a series of conditional bit operations. Nicely, the "FE" exception bits are all a uniform offset from the FPSCR enable bits, so the bit-by-bit operation can instead be performed by a shift with appropriate masking. --- ChangeLog | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'ChangeLog') diff --git a/ChangeLog b/ChangeLog index 37c2ff3280..c2d70717ec 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,12 @@ +2019-08-28 Paul A. Clarke + + * sysdeps/powerpc/fpu/fenv_libc.h: Define FPSCR bitmasks. + (fenv_reg_to_exceptions): Replace bitwise operations with mask-shift. + (fenv_exceptions_to_reg): New. + * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Replace bitwise + operation with call to fenv_exceptions_to_reg(). + * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise. + 2019-08-28 Florian Weimer * misc/mntent.c (struct mntent_buffer): Define. -- cgit v1.2.3