From f53ffc9b90cbd92fa5518686daf4091bdd1d4889 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sat, 6 Mar 2021 10:19:32 -0800 Subject: x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444] commit 2d651eb9265d1366d7b9e881bfddd46db9c1ecc4 Author: H.J. Lu Date: Fri Sep 18 07:55:14 2020 -0700 x86: Move x86 processor cache info to cpu_features missed _SC_LEVEL1_ICACHE_LINESIZE. 1. Add level1_icache_linesize to struct cpu_features. 2. Initialize level1_icache_linesize by calling handle_intel, handle_zhaoxin and handle_amd with _SC_LEVEL1_ICACHE_LINESIZE. 3. Return level1_icache_linesize for _SC_LEVEL1_ICACHE_LINESIZE. Reviewed-by: Carlos O'Donell --- sysdeps/x86/include/cpu-features.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'sysdeps/x86/include') diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index c5a779ba32..d042a2ebef 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -876,6 +876,8 @@ struct cpu_features unsigned long int rep_stosb_threshold; /* _SC_LEVEL1_ICACHE_SIZE. */ unsigned long int level1_icache_size; + /* _SC_LEVEL1_ICACHE_LINESIZE. */ + unsigned long int level1_icache_linesize; /* _SC_LEVEL1_DCACHE_SIZE. */ unsigned long int level1_dcache_size; /* _SC_LEVEL1_DCACHE_ASSOC. */ -- cgit v1.2.3