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authorAndrew Senkevich <andrew.senkevich@intel.com>2015-06-09 18:29:47 +0300
committerAndrew Senkevich <andrew.senkevich@intel.com>2015-06-09 18:29:47 +0300
commit04f496d6025753058bdd071fd711e9f56df149a7 (patch)
tree21b047c3aadb643a0eb86e277e496146bd9b5f84
parent24a2718f595bc11dc6abb31303ceb8fdcb664f2f (diff)
downloadglibc-04f496d6025753058bdd071fd711e9f56df149a7.tar.xz
glibc-04f496d6025753058bdd071fd711e9f56df149a7.zip
Vector cosf for x86_64.
Here is implementation of vectorized cosf containing SSE, AVX, AVX2 and AVX512 versions according to Vector ABI <https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>. * sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files. * sysdeps/x86_64/fpu/Versions: New versions added. * sysdeps/x86_64/fpu/svml_s_cosf4_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core_sse4.S: New file. * sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S: New file. * sysdeps/x86_64/fpu/svml_s_cosf8_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core_avx2.S: New file. * sysdeps/x86_64/fpu/svml_s_cosf16_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S: New file. * sysdeps/x86_64/fpu/svml_s_wrapper_impl.h: New file. * sysdeps/x86_64/fpu/svml_s_cosf_data.S: New file. * sysdeps/x86_64/fpu/svml_s_cosf_data.h: New file. * sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added build of SSE, AVX2 and AVX512 IFUNC versions. * sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added. * sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration for cosf. * NEWS: Mention addition of x86_64 vector cosf.
-rw-r--r--ChangeLog21
-rw-r--r--NEWS2
-rw-r--r--sysdeps/unix/sysv/linux/x86_64/libmvec.abilist4
-rw-r--r--sysdeps/x86/fpu/bits/math-vector.h2
-rw-r--r--sysdeps/x86_64/fpu/Makefile4
-rw-r--r--sysdeps/x86_64/fpu/Versions1
-rw-r--r--sysdeps/x86_64/fpu/multiarch/Makefile3
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S39
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S460
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S38
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core_sse4.S227
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S38
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core_avx2.S215
-rw-r--r--sysdeps/x86_64/fpu/svml_s_cosf16_core.S25
-rw-r--r--sysdeps/x86_64/fpu/svml_s_cosf4_core.S29
-rw-r--r--sysdeps/x86_64/fpu/svml_s_cosf8_core.S29
-rw-r--r--sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S25
-rw-r--r--sysdeps/x86_64/fpu/svml_s_cosf_data.S1130
-rw-r--r--sysdeps/x86_64/fpu/svml_s_cosf_data.h58
-rw-r--r--sysdeps/x86_64/fpu/svml_s_wrapper_impl.h111
20 files changed, 2458 insertions, 3 deletions
diff --git a/ChangeLog b/ChangeLog
index 47318a709b..c3e52b25a9 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -47,6 +47,27 @@
* sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: New file.
* sysdeps/x86_64/fpu/test-double-vlen8.c: New file.
+ * sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
+ * sysdeps/x86_64/fpu/Versions: New versions added.
+ * sysdeps/x86_64/fpu/svml_s_cosf4_core.S: New file.
+ * sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S: New file.
+ * sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core_sse4.S: New file.
+ * sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S: New file.
+ * sysdeps/x86_64/fpu/svml_s_cosf8_core.S: New file.
+ * sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S: New file.
+ * sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core_avx2.S: New file.
+ * sysdeps/x86_64/fpu/svml_s_cosf16_core.S: New file.
+ * sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S: New file.
+ * sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S: New file.
+ * sysdeps/x86_64/fpu/svml_s_wrapper_impl.h: New file.
+ * sysdeps/x86_64/fpu/svml_s_cosf_data.S: New file.
+ * sysdeps/x86_64/fpu/svml_s_cosf_data.h: New file.
+ * sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
+ build of SSE, AVX2 and AVX512 IFUNC versions.
+ * sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added.
+ * sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration for cosf.
+ * NEWS: Mention addition of x86_64 vector cosf.
+
2015-06-09 Marko Myllynen <myllynen@redhat.com>
* locale/C-ctype.c (PREDEFINED_CLASSES): Remove.
diff --git a/NEWS b/NEWS
index 5e223a1e39..53f244d80f 100644
--- a/NEWS
+++ b/NEWS
@@ -52,7 +52,7 @@ Version 2.22
condition in some applications.
* Added vector math library named libmvec with the following vectorized x86_64
- implementations: cos.
+ implementations: cos, cosf.
The library can be disabled with --disable-mathvec. Use of the functions is
enabled with -fopenmp -ffast-math starting from -O1 for GCC version >= 4.9.0.
The library is linked in as needed when using -lm (no need to specify -lmvec
diff --git a/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist b/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist
index be6eaedafd..acabb8ae3a 100644
--- a/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist
@@ -1,6 +1,10 @@
GLIBC_2.22
GLIBC_2.22 A
_ZGVbN2v_cos F
+ _ZGVbN4v_cosf F
_ZGVcN4v_cos F
+ _ZGVcN8v_cosf F
_ZGVdN4v_cos F
+ _ZGVdN8v_cosf F
+ _ZGVeN16v_cosf F
_ZGVeN8v_cos F
diff --git a/sysdeps/x86/fpu/bits/math-vector.h b/sysdeps/x86/fpu/bits/math-vector.h
index 27294ce9fa..b3ef8330e8 100644
--- a/sysdeps/x86/fpu/bits/math-vector.h
+++ b/sysdeps/x86/fpu/bits/math-vector.h
@@ -30,5 +30,7 @@
# define __DECL_SIMD_x86_64 _Pragma ("omp declare simd notinbranch")
# undef __DECL_SIMD_cos
# define __DECL_SIMD_cos __DECL_SIMD_x86_64
+# undef __DECL_SIMD_cosf
+# define __DECL_SIMD_cosf __DECL_SIMD_x86_64
# endif
#endif
diff --git a/sysdeps/x86_64/fpu/Makefile b/sysdeps/x86_64/fpu/Makefile
index 2d5fcf894c..af0d2af261 100644
--- a/sysdeps/x86_64/fpu/Makefile
+++ b/sysdeps/x86_64/fpu/Makefile
@@ -1,7 +1,9 @@
ifeq ($(subdir),mathvec)
libmvec-support += svml_d_cos2_core svml_d_cos4_core_avx \
svml_d_cos4_core svml_d_cos8_core \
- svml_d_cos_data init-arch
+ svml_d_cos_data svml_s_cosf4_core svml_s_cosf8_core_avx \
+ svml_s_cosf8_core svml_s_cosf16_core svml_s_cosf_data \
+ init-arch
endif
# Variables for libmvec tests.
diff --git a/sysdeps/x86_64/fpu/Versions b/sysdeps/x86_64/fpu/Versions
index 4290e73589..f85c28b924 100644
--- a/sysdeps/x86_64/fpu/Versions
+++ b/sysdeps/x86_64/fpu/Versions
@@ -1,5 +1,6 @@
libmvec {
GLIBC_2.22 {
_ZGVbN2v_cos; _ZGVcN4v_cos; _ZGVdN4v_cos; _ZGVeN8v_cos;
+ _ZGVbN4v_cosf; _ZGVcN8v_cosf; _ZGVdN8v_cosf; _ZGVeN16v_cosf;
}
}
diff --git a/sysdeps/x86_64/fpu/multiarch/Makefile b/sysdeps/x86_64/fpu/multiarch/Makefile
index b2f3266490..6b50475a2a 100644
--- a/sysdeps/x86_64/fpu/multiarch/Makefile
+++ b/sysdeps/x86_64/fpu/multiarch/Makefile
@@ -54,5 +54,6 @@ endif
ifeq ($(subdir),mathvec)
libmvec-sysdep_routines += svml_d_cos2_core_sse4 svml_d_cos4_core_avx2 \
- svml_d_cos8_core_avx512
+ svml_d_cos8_core_avx512 svml_s_cosf4_core_sse4 \
+ svml_s_cosf8_core_avx2 svml_s_cosf16_core_avx512
endif
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S
new file mode 100644
index 0000000000..91564de22a
--- /dev/null
+++ b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S
@@ -0,0 +1,39 @@
+/* Multiple versions of vectorized cosf.
+ Copyright (C) 2014-2015 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <sysdep.h>
+#include <init-arch.h>
+
+ .text
+ENTRY (_ZGVeN16v_cosf)
+ .type _ZGVeN16v_cosf, @gnu_indirect_function
+ cmpl $0, KIND_OFFSET+__cpu_features(%rip)
+ jne 1
+ call __init_cpu_features
+1: leaq _ZGVeN16v_cosf_skx(%rip), %rax
+ testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
+ jnz 3
+2: leaq _ZGVeN16v_cosf_knl(%rip), %rax
+ testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
+ jnz 3
+ leaq _ZGVeN16v_cosf_avx2_wrapper(%rip), %rax
+3: ret
+END (_ZGVeN16v_cosf)
+
+#define _ZGVeN16v_cosf _ZGVeN16v_cosf_avx2_wrapper
+#include "../svml_s_cosf16_core.S"
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S
new file mode 100644
index 0000000000..a78ae2ee7e
--- /dev/null
+++ b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S
@@ -0,0 +1,460 @@
+/* Function cosf vectorized with AVX-512. KNL and SKX versions.
+ Copyright (C) 2014-2015 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <sysdep.h>
+#include "svml_s_cosf_data.h"
+#include "svml_s_wrapper_impl.h"
+
+ .text
+ENTRY (_ZGVeN16v_cosf_knl)
+#ifndef HAVE_AVX512_ASM_SUPPORT
+WRAPPER_IMPL_AVX512 _ZGVdN8v_cosf
+#else
+/*
+ ALGORITHM DESCRIPTION:
+
+ 1) Range reduction to [-Pi/2; +Pi/2] interval
+ a) We remove sign using AND operation
+ b) Add Pi/2 value to argument X for Cos to Sin transformation
+ c) Getting octant Y by 1/Pi multiplication
+ d) Add "Right Shifter" value
+ e) Treat obtained value as integer for destination sign setting.
+ Shift first bit of this value to the last (sign) position
+ f) Subtract "Right Shifter" value
+ g) Subtract 0.5 from result for octant correction
+ h) Subtract Y*PI from X argument, where PI divided to 4 parts:
+ X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4;
+ 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval)
+ a) Calculate X^2 = X * X
+ b) Calculate polynomial:
+ R = X + X * X^2 * (A3 + x^2 * (A5 + .....
+ 3) Destination sign setting
+ a) Set shifted destination sign using XOR operation:
+ R = XOR( R, S );
+ */
+ pushq %rbp
+ cfi_adjust_cfa_offset (8)
+ cfi_rel_offset (%rbp, 0)
+ movq %rsp, %rbp
+ cfi_def_cfa_register (%rbp)
+ andq $-64, %rsp
+ subq $1280, %rsp
+ movq __svml_scos_data@GOTPCREL(%rip), %rdx
+
+/*
+ h) Subtract Y*PI from X argument, where PI divided to 4 parts:
+ X = X - Y*PI1 - Y*PI2 - Y*PI3
+ */
+ vmovaps %zmm0, %zmm6
+ movl $-1, %eax
+
+/* b) Add Pi/2 value to argument X for Cos to Sin transformation */
+ vaddps __sHalfPI(%rdx), %zmm0, %zmm2
+ vmovups __sRShifter(%rdx), %zmm3
+
+/*
+ 1) Range reduction to [-Pi/2; +Pi/2] interval
+ c) Getting octant Y by 1/Pi multiplication
+ d) Add "Right Shifter" (0x4B000000) value
+ */
+ vfmadd132ps __sInvPI(%rdx), %zmm3, %zmm2
+ vmovups __sPI1_FMA(%rdx), %zmm5
+
+/* f) Subtract "Right Shifter" (0x4B000000) value */
+ vsubps %zmm3, %zmm2, %zmm4
+ vmovups __sA9_FMA(%rdx), %zmm9
+
+/* Check for large and special arguments */
+ vpandd __sAbsMask(%rdx), %zmm0, %zmm1
+
+/*
+ e) Treat obtained value as integer for destination sign setting.
+ Shift first bit of this value to the last (sign) position (S << 31)
+ */
+ vpslld $31, %zmm2, %zmm8
+ vcmpps $22, __sRangeReductionVal(%rdx), %zmm1, %k1
+ vpbroadcastd %eax, %zmm12{%k1}{z}
+
+/* g) Subtract 0.5 from result for octant correction */
+ vsubps __sOneHalf(%rdx), %zmm4, %zmm7
+ vptestmd %zmm12, %zmm12, %k0
+ vfnmadd231ps %zmm7, %zmm5, %zmm6
+ kmovw %k0, %ecx
+ vfnmadd231ps __sPI2_FMA(%rdx), %zmm7, %zmm6
+ vfnmadd132ps __sPI3_FMA(%rdx), %zmm6, %zmm7
+
+/* a) Calculate X^2 = X * X */
+ vmulps %zmm7, %zmm7, %zmm10
+
+/*
+ 3) Destination sign setting
+ a) Set shifted destination sign using XOR operation:
+ R = XOR( R, S );
+ */
+ vpxord %zmm8, %zmm7, %zmm11
+
+/*
+ b) Calculate polynomial:
+ R = X + X * X^2 * (A3 + x^2 * (A5 + x^2 * (A7 + x^2 * (A9))));
+ */
+ vfmadd213ps __sA7_FMA(%rdx), %zmm10, %zmm9
+ vfmadd213ps __sA5_FMA(%rdx), %zmm10, %zmm9
+ vfmadd213ps __sA3(%rdx), %zmm10, %zmm9
+ vmulps %zmm10, %zmm9, %zmm1
+ vfmadd213ps %zmm11, %zmm11, %zmm1
+ testl %ecx, %ecx
+ jne .LBL_1_3
+
+.LBL_1_2:
+ cfi_remember_state
+ vmovaps %zmm1, %zmm0
+ movq %rbp, %rsp
+ cfi_def_cfa_register (%rsp)
+ popq %rbp
+ cfi_adjust_cfa_offset (-8)
+ cfi_restore (%rbp)
+ ret
+
+.LBL_1_3:
+ cfi_restore_state
+ vmovups %zmm0, 1152(%rsp)
+ vmovups %zmm1, 1216(%rsp)
+ je .LBL_1_2
+
+ xorb %dl, %dl
+ kmovw %k4, 1048(%rsp)
+ xorl %eax, %eax
+ kmovw %k5, 1040(%rsp)
+ kmovw %k6, 1032(%rsp)
+ kmovw %k7, 1024(%rsp)
+ vmovups %zmm16, 960(%rsp)
+ vmovups %zmm17, 896(%rsp)
+ vmovups %zmm18, 832(%rsp)
+ vmovups %zmm19, 768(%rsp)
+ vmovups %zmm20, 704(%rsp)
+ vmovups %zmm21, 640(%rsp)
+ vmovups %zmm22, 576(%rsp)
+ vmovups %zmm23, 512(%rsp)
+ vmovups %zmm24, 448(%rsp)
+ vmovups %zmm25, 384(%rsp)
+ vmovups %zmm26, 320(%rsp)
+ vmovups %zmm27, 256(%rsp)
+ vmovups %zmm28, 192(%rsp)
+ vmovups %zmm29, 128(%rsp)
+ vmovups %zmm30, 64(%rsp)
+ vmovups %zmm31, (%rsp)
+ movq %rsi, 1064(%rsp)
+ movq %rdi, 1056(%rsp)
+ movq %r12, 1096(%rsp)
+ cfi_offset_rel_rsp (12, 1096)
+ movb %dl, %r12b
+ movq %r13, 1088(%rsp)
+ cfi_offset_rel_rsp (13, 1088)
+ movl %ecx, %r13d
+ movq %r14, 1080(%rsp)
+ cfi_offset_rel_rsp (14, 1080)
+ movl %eax, %r14d
+ movq %r15, 1072(%rsp)
+ cfi_offset_rel_rsp (15, 1072)
+ cfi_remember_state
+
+.LBL_1_6:
+ btl %r14d, %r13d
+ jc .LBL_1_12
+
+.LBL_1_7:
+ lea 1(%r14), %esi
+ btl %esi, %r13d
+ jc .LBL_1_10
+
+.LBL_1_8:
+ addb $1, %r12b
+ addl $2, %r14d
+ cmpb $16, %r12b
+ jb .LBL_1_6
+
+ kmovw 1048(%rsp), %k4
+ movq 1064(%rsp), %rsi
+ kmovw 1040(%rsp), %k5
+ movq 1056(%rsp), %rdi
+ kmovw 1032(%rsp), %k6
+ movq 1096(%rsp), %r12
+ cfi_restore (%r12)
+ movq 1088(%rsp), %r13
+ cfi_restore (%r13)
+ kmovw 1024(%rsp), %k7
+ vmovups 960(%rsp), %zmm16
+ vmovups 896(%rsp), %zmm17
+ vmovups 832(%rsp), %zmm18
+ vmovups 768(%rsp), %zmm19
+ vmovups 704(%rsp), %zmm20
+ vmovups 640(%rsp), %zmm21
+ vmovups 576(%rsp), %zmm22
+ vmovups 512(%rsp), %zmm23
+ vmovups 448(%rsp), %zmm24
+ vmovups 384(%rsp), %zmm25
+ vmovups 320(%rsp), %zmm26
+ vmovups 256(%rsp), %zmm27
+ vmovups 192(%rsp), %zmm28
+ vmovups 128(%rsp), %zmm29
+ vmovups 64(%rsp), %zmm30
+ vmovups (%rsp), %zmm31
+ movq 1080(%rsp), %r14
+ cfi_restore (%r14)
+ movq 1072(%rsp), %r15
+ cfi_restore (%r15)
+ vmovups 1216(%rsp), %zmm1
+ jmp .LBL_1_2
+
+.LBL_1_10:
+ cfi_restore_state
+ movzbl %r12b, %r15d
+ vmovss 1156(%rsp,%r15,8), %xmm0
+ call cosf@PLT
+ vmovss %xmm0, 1220(%rsp,%r15,8)
+ jmp .LBL_1_8
+
+.LBL_1_12:
+ movzbl %r12b, %r15d
+ vmovss 1152(%rsp,%r15,8), %xmm0
+ call cosf@PLT
+ vmovss %xmm0, 1216(%rsp,%r15,8)
+ jmp .LBL_1_7
+#endif
+END (_ZGVeN16v_cosf_knl)
+
+ENTRY (_ZGVeN16v_cosf_skx)
+#ifndef HAVE_AVX512_ASM_SUPPORT
+WRAPPER_IMPL_AVX512 _ZGVdN8v_cosf
+#else
+/*
+ ALGORITHM DESCRIPTION:
+
+ 1) Range reduction to [-Pi/2; +Pi/2] interval
+ a) We remove sign using AND operation
+ b) Add Pi/2 value to argument X for Cos to Sin transformation
+ c) Getting octant Y by 1/Pi multiplication
+ d) Add "Right Shifter" value
+ e) Treat obtained value as integer for destination sign setting.
+ Shift first bit of this value to the last (sign) position
+ f) Subtract "Right Shifter" value
+ g) Subtract 0.5 from result for octant correction
+ h) Subtract Y*PI from X argument, where PI divided to 4 parts:
+ X = X - Y*PI1 - Y*PI2 - Y*PI3 - Y*PI4;
+ 2) Polynomial (minimax for sin within [-Pi/2; +Pi/2] interval)
+ a) Calculate X^2 = X * X
+ b) Calculate polynomial:
+ R = X + X * X^2 * (A3 + x^2 * (A5 + .....
+ 3) Destination sign setting
+ a) Set shifted destination sign using XOR operation:
+ R = XOR( R, S );
+ */
+ pushq %rbp
+ cfi_adjust_cfa_offset (8)
+ cfi_rel_offset (%rbp, 0)
+ movq %rsp, %rbp
+ cfi_def_cfa_register (%rbp)
+ andq $-64, %rsp
+ subq $1280, %rsp
+ movq __svml_scos_data@GOTPCREL(%rip), %rax
+
+/*
+ h) Subtract Y*PI from X argument, where PI divided to 4 parts:
+ X = X - Y*PI1 - Y*PI2 - Y*PI3
+ */
+ vmovaps %zmm0, %zmm6
+ vmovups .L_2il0floatpacket.13(%rip), %zmm12
+ vmovups __sRShifter(%rax), %zmm3
+ vmovups __sPI1_FMA(%rax), %zmm5
+ vmovups __sA9_FMA(%rax), %zmm9
+
+/* b) Add Pi/2 value to argument X for Cos to Sin transformation */
+ vaddps __sHalfPI(%rax), %zmm0, %zmm2
+
+/* Check for large and special arguments */
+ vandps __sAbsMask(%rax), %zmm0, %zmm1
+
+/*
+ 1) Range reduction to [-Pi/2; +Pi/2] interval
+ c) Getting octant Y by 1/Pi multiplication
+ d) Add "Right Shifter" (0x4B000000) value
+ */
+ vfmadd132ps __sInvPI(%rax), %zmm3, %zmm2
+ vcmpps $18, __sRangeReductionVal(%rax), %zmm1, %k1
+
+/*
+ e) Treat obtained value as integer for destination sign setting.
+ Shift first bit of this value to the last (sign) position (S << 31)
+ */
+ vpslld $31, %zmm2, %zmm8
+
+/* f) Subtract "Right Shifter" (0x4B000000) value */
+ vsubps %zmm3, %zmm2, %zmm4
+
+/* g) Subtract 0.5 from result for octant correction */
+ vsubps __sOneHalf(%rax), %zmm4, %zmm7
+ vfnmadd231ps %zmm7, %zmm5, %zmm6
+ vfnmadd231ps __sPI2_FMA(%rax), %zmm7, %zmm6
+ vfnmadd132ps __sPI3_FMA(%rax), %zmm6, %zmm7
+
+/* a) Calculate X^2 = X * X */
+ vmulps %zmm7, %zmm7, %zmm10
+
+/*
+ 3) Destination sign setting
+ a) Set shifted destination sign using XOR operation:
+ R = XOR( R, S );
+ */
+ vxorps %zmm8, %zmm7, %zmm11
+
+/*
+ b) Calculate polynomial:
+ R = X + X * X^2 * (A3 + x^2 * (A5 + x^2 * (A7 + x^2 * (A9))));
+ */
+ vfmadd213ps __sA7_FMA(%rax), %zmm10, %zmm9
+ vfmadd213ps __sA5_FMA(%rax), %zmm10, %zmm9
+ vfmadd213ps __sA3(%rax), %zmm10, %zmm9
+ vpandnd %zmm1, %zmm1, %zmm12{%k1}
+ vmulps %zmm10, %zmm9, %zmm1
+ vptestmd %zmm12, %zmm12, %k0