Fix spelling errors in sysdeps/powerpc files.

43 files changed, 167 insertions, 121 deletions

diff --git a/ChangeLog b/ChangeLog
index 1d0ff3e631..b0e45aea5b 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,49 @@
+2013-01-07  Anton Blanchard  <anton@samba.org>
+
+	* sysdeps/powerpc/fpu/feholdexcpt.c: Fixed spelling errors.
+	* sysdeps/powerpc/fpu/feupdateenv.c: Likewise.
+	* sysdeps/powerpc/fpu/math_ldbl.h: Likewise.
+	* sysdeps/powerpc/powerpc32/bits/atomic.h: Likewise.
+	* sysdeps/powerpc/powerpc32/cell/memcpy.S: Likewise.
+	* sysdeps/powerpc/powerpc32/dl-machine.c: Likewise.
+	* sysdeps/powerpc/powerpc32/dl-start.S: Likewise.
+	* sysdeps/powerpc/powerpc32/memset.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power4/fpu/mpa.c: Likewise.
+	* sysdeps/powerpc/powerpc32/power4/fpu/slowpow.c: Likewise.
+	* sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power4/hp-timing.h: Likewise.
+	* sysdeps/powerpc/powerpc32/power4/memcmp.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power4/strncmp.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power5/fpu/w_sqrt.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power5/fpu/w_sqrtf.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power6/memcpy.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power7/memchr.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power7/memcmp.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power7/memrchr.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power7/strcasecmp.S: Likewise.
+	* sysdeps/powerpc/powerpc32/power7/strncmp.S: Likewise.
+	* sysdeps/powerpc/powerpc32/strncmp.S: Likewise.
+	* sysdeps/powerpc/powerpc64/bits/atomic.h: Likewise.
+	* sysdeps/powerpc/powerpc64/cell/memcpy.S: Likewise.
+	* sysdeps/powerpc/powerpc64/dl-machine.h: Likewise.
+	* sysdeps/powerpc/powerpc64/fpu/s_ceill.S: Likewise.
+	* sysdeps/powerpc/powerpc64/fpu/s_nearbyintl.S: Likewise.
+	* sysdeps/powerpc/powerpc64/hp-timing.h: Likewise.
+	* sysdeps/powerpc/powerpc64/memcpy.S: Likewise.
+	* sysdeps/powerpc/powerpc64/power4/fpu/mpa.c: Likewise.
+	* sysdeps/powerpc/powerpc64/power4/fpu/slowpow.c: Likewise.
+	* sysdeps/powerpc/powerpc64/power4/memcmp.S: Likewise.
+	* sysdeps/powerpc/powerpc64/power4/memcpy.S: Likewise.
+	* sysdeps/powerpc/powerpc64/power4/strncmp.S: Likewise.
+	* sysdeps/powerpc/powerpc64/power6/memcpy.S: Likewise.
+	* sysdeps/powerpc/powerpc64/power7/memchr.S: Likewise.
+	* sysdeps/powerpc/powerpc64/power7/memcmp.S: Likewise.
+	* sysdeps/powerpc/powerpc64/power7/memrchr.S: Likewise.
+	* sysdeps/powerpc/powerpc64/power7/strcasecmp.S: Likewise.
+	* sysdeps/powerpc/powerpc64/power7/strncmp.S: Likewise.
+	* sysdeps/powerpc/powerpc64/strncmp.S: Likewise.
+
 2013-01-07  Joseph Myers  <joseph@codesourcery.com>
 
 	* malloc/malloc.h (__MALLOC_P): Remove all definitions.
diff --git a/sysdeps/powerpc/fpu/feholdexcpt.c b/sysdeps/powerpc/fpu/feholdexcpt.c
index c91645560a..671724b287 100644
--- a/sysdeps/powerpc/fpu/feholdexcpt.c
+++ b/sysdeps/powerpc/fpu/feholdexcpt.c
@@ -33,7 +33,7 @@ feholdexcept (fenv_t *envp)
   new.l[1] = old.l[1] & 7;
   new.l[0] = old.l[0];
   
-  /* If the old env had any eabled exceptions, then mask SIGFPE in the
+  /* If the old env had any enabled exceptions, then mask SIGFPE in the
      MSR FE0/FE1 bits.  This may allow the FPU to run faster because it
      always takes the default action and can not generate SIGFPE. */
   if ((old.l[1] & _FPU_MASK_ALL) != 0)
diff --git a/sysdeps/powerpc/fpu/feupdateenv.c b/sysdeps/powerpc/fpu/feupdateenv.c
index 30f8a6b6c6..66f2826398 100644
--- a/sysdeps/powerpc/fpu/feupdateenv.c
+++ b/sysdeps/powerpc/fpu/feupdateenv.c
@@ -37,14 +37,14 @@ __feupdateenv (const fenv_t *envp)
      unchanged.  */
   new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF);
   
-  /* If the old env has no eabled exceptions and the new env has any enabled
+  /* If the old env has no enabled exceptions and the new env has any enabled
      exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put
      the hardware into "precise mode" and may cause the FPU to run slower on
      some hardware.  */
   if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
     (void)__fe_nomask_env ();
   
-  /* If the old env had any eabled exceptions and the new env has no enabled
+  /* If the old env had any enabled exceptions and the new env has no enabled
      exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
      FPU to run faster because it always takes the default action and can not 
      generate SIGFPE. */
diff --git a/sysdeps/powerpc/fpu/math_ldbl.h b/sysdeps/powerpc/fpu/math_ldbl.h
index 6cd6d0bdfe..20224e6646 100644
--- a/sysdeps/powerpc/fpu/math_ldbl.h
+++ b/sysdeps/powerpc/fpu/math_ldbl.h
@@ -27,7 +27,7 @@ ldbl_extract_mantissa (int64_t *hi64, u_int64_t *lo64, int *exp, long double x)
       lo |= (1ULL << 52);
       lo = lo << 7; /* pre-shift lo to match ieee854.  */
       /* The lower double is normalized separately from the upper.  We
-	 may need to adjust the lower manitissa to reflect this.  */
+	 may need to adjust the lower mantissa to reflect this.  */
       ediff = eldbl.ieee.exponent - eldbl.ieee.exponent2;
       if (ediff > 53)
 	lo = lo >> (ediff-53);
diff --git a/sysdeps/powerpc/powerpc32/bits/atomic.h b/sysdeps/powerpc/powerpc32/bits/atomic.h
index 2f441ed985..3e3a1effe5 100644
--- a/sysdeps/powerpc/powerpc32/bits/atomic.h
+++ b/sysdeps/powerpc/powerpc32/bits/atomic.h
@@ -21,7 +21,7 @@
     This is a hint to the hardware to expect additional updates adjacent
     to the lock word or not.  If we are acquiring a Mutex, the hint
     should be true. Otherwise we releasing a Mutex or doing a simple
-    atomic operation.  In that case we don't expect addtional updates
+    atomic operation.  In that case we don't expect additional updates
     adjacent to the lock word after the Store Conditional and the hint
     should be false.  */
     
@@ -35,7 +35,7 @@
 
 /*
  * The 32-bit exchange_bool is different on powerpc64 because the subf
- * does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
+ * does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
  * (a load word and zero (high 32) form).  So powerpc64 has a slightly
  * different version in sysdeps/powerpc/powerpc64/bits/atomic.h.
  */
diff --git a/sysdeps/powerpc/powerpc32/cell/memcpy.S b/sysdeps/powerpc/powerpc32/cell/memcpy.S
index 5fbdab1db4..6d7d4ce5db 100644
--- a/sysdeps/powerpc/powerpc32/cell/memcpy.S
+++ b/sysdeps/powerpc/powerpc32/cell/memcpy.S
@@ -34,7 +34,7 @@
  * latency to memory is >400 clocks
  * To improve copy performance we need to prefetch source data
  * far ahead to hide this latency
- * For best performance instructionforms ending in "." like "andi."
+ * For best performance instruction forms ending in "." like "andi."
  * should be avoided as the are implemented in microcode on CELL.
  * The below code is loop unrolled for the CELL cache line of 128 bytes
  */
@@ -146,7 +146,7 @@ EALIGN (BP_SYM (memcpy), 5, 0)
 	lfd	fp9, 0x08(r4)
 	dcbz	r11,r6
 	lfd	fp10, 0x10(r4)	/* 4 register stride copy is optimal  */
-	lfd	fp11, 0x18(r4)	/* to hide 1st level cache lantency.  */
+	lfd	fp11, 0x18(r4)	/* to hide 1st level cache latency.  */
 	lfd	fp12, 0x20(r4)
 	stfd	fp9, 0x08(r6)
 	stfd	fp10, 0x10(r6)
diff --git a/sysdeps/powerpc/powerpc32/dl-machine.c b/sysdeps/powerpc/powerpc32/dl-machine.c
index f9f2a5d8f3..bd42fdf7d5 100644
--- a/sysdeps/powerpc/powerpc32/dl-machine.c
+++ b/sysdeps/powerpc/powerpc32/dl-machine.c
@@ -113,7 +113,7 @@ __elf_preferred_address (struct link_map *loader, size_t maplength,
   /* Otherwise, quickly look for a suitable gap between 0x3FFFF and
      0x70000000.  0x3FFFF is so that references off NULL pointers will
      cause a segfault, 0x70000000 is just paranoia (it should always
-     be superceded by the program's load address).  */
+     be superseded by the program's load address).  */
   low =  0x0003FFFF;
   high = 0x70000000;
   for (nsid = 0; nsid < DL_NNS; ++nsid)
diff --git a/sysdeps/powerpc/powerpc32/dl-start.S b/sysdeps/powerpc/powerpc32/dl-start.S
index 01484e8e94..fa9c9bc4ae 100644
--- a/sysdeps/powerpc/powerpc32/dl-start.S
+++ b/sysdeps/powerpc/powerpc32/dl-start.S
@@ -74,7 +74,7 @@ _dl_start_user:
 	slwi	r5,r3,2
 	add	r6,r4,r5
 	addi	r5,r6,4
-/* pass the auxilary vector in r6. This is passed to us just after _envp.  */
+/* pass the auxiliary vector in r6. This is passed to us just after _envp.  */
 2:	lwzu	r0,4(r6)
 	cmpwi	r0,0
 	bne	2b
diff --git a/sysdeps/powerpc/powerpc32/memset.S b/sysdeps/powerpc/powerpc32/memset.S
index 2e86d1c910..45c79d858b 100644
--- a/sysdeps/powerpc/powerpc32/memset.S
+++ b/sysdeps/powerpc/powerpc32/memset.S
@@ -275,7 +275,7 @@ L(checklinesize):
 	beq	cr1,L(nondcbz)
 
 /* If the cache line size is 32 bytes then goto to L(zloopstart),
-   which is coded specificly for 32-byte lines (and 601).  */
+   which is coded specifically for 32-byte lines (and 601).  */
 	cmplwi	cr1,rCLS,32
 	beq	cr1,L(zloopstart)
 
diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/mpa.c b/sysdeps/powerpc/powerpc32/power4/fpu/mpa.c
index f167969ea3..b6f8341afa 100644
--- a/sysdeps/powerpc/powerpc32/power4/fpu/mpa.c
+++ b/sysdeps/powerpc/powerpc32/power4/fpu/mpa.c
@@ -409,9 +409,9 @@ void __mul(const mp_no *x, const mp_no *y, mp_no *z, int p) {
     if (k > p2)  {i1=k-p2; i2=p2+1; }
     else        {i1=1;   i2=k;   }
 #if 1
-    /* rearange this inner loop to allow the fmadd instructions to be
+    /* rearrange this inner loop to allow the fmadd instructions to be
        independent and execute in parallel on processors that have
-       dual symetrical FP pipelines.  */
+       dual symmetrical FP pipelines.  */
     if (i1 < (i2-1))
     {
 	/* make sure we have at least 2 iterations */
@@ -437,7 +437,7 @@ void __mul(const mp_no *x, const mp_no *y, mp_no *z, int p) {
 	zk += x->d[i1]*y->d[i1];
     }
 #else
-    /* The orginal code.  */
+    /* The original code.  */
     for (i=i1,j=i2-1; i<i2; i++,j--)  zk += X[i]*Y[j];
 #endif
 
diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/slowpow.c b/sysdeps/powerpc/powerpc32/power4/fpu/slowpow.c
index 098e19a5f0..7c97d95817 100644
--- a/sysdeps/powerpc/powerpc32/power4/fpu/slowpow.c
+++ b/sysdeps/powerpc/powerpc32/power4/fpu/slowpow.c
@@ -59,7 +59,7 @@ __slowpow (double x, double y, double z)
   res1 = (double) (ldpp - ldeps);
 
   if (res != res1)		/* if result still not accurate enough */
-    {				/* use mpa for higher persision.  */
+    {				/* use mpa for higher precision.  */
       mp_no mpx, mpy, mpz, mpw, mpp, mpr, mpr1;
       static const mp_no eps = { -3, {1.0, 4.0} };
       int p;
diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S
index cb55816204..4f1c17680d 100644
--- a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S
+++ b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrt.S
@@ -22,7 +22,7 @@
 /* double [fp1] sqrt (double x [fp1])
    Power4 (ISA V2.0) and above implement sqrt in hardware (not optional).
    The fsqrt instruction generates the correct value for all inputs and
-   sets the appropriate floating point exceptions.  Extented checking is
+   sets the appropriate floating point exceptions.  Extended checking is
    only needed to set errno (via __kernel_standard) if the input value
    is negative.
    
diff --git a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S
index a13a846875..0da5b7a8e3 100644
--- a/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S
+++ b/sysdeps/powerpc/powerpc32/power4/fpu/w_sqrtf.S
@@ -22,7 +22,7 @@
 /* float [fp1] sqrts (float x [fp1])
    Power4 (ISA V2.0) and above implement sqrt in hardware (not optional).
    The fsqrts instruction generates the correct value for all inputs and
-   sets the appropriate floating point exceptions.  Extented checking is
+   sets the appropriate floating point exceptions.  Extended checking is
    only needed to set errno (via __kernel_standard) if the input value
    is negative.
    
diff --git a/sysdeps/powerpc/powerpc32/power4/hp-timing.h b/sysdeps/powerpc/powerpc32/power4/hp-timing.h
index 4742d76242..7d6c96e9e9 100644
--- a/sysdeps/powerpc/powerpc32/power4/hp-timing.h
+++ b/sysdeps/powerpc/powerpc32/power4/hp-timing.h
@@ -82,7 +82,7 @@ typedef unsigned long long int hp_timing_t;
 /* That's quite simple.  Use the `mftb' instruction.  Note that the value
    might not be 100% accurate since there might be some more instructions
    running in this moment.  This could be changed by using a barrier like
-   'lwsync' right before the `mftb' instruciton.  But we are not interested
+   'lwsync' right before the `mftb' instruction.  But we are not interested
    in accurate clock cycles here so we don't do this.  */
 
 #define HP_TIMING_NOW(Var)						\
diff --git a/sysdeps/powerpc/powerpc