aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorSunil K Pandey <skpgkp2@gmail.com>2021-12-29 09:05:18 -0800
committerSunil K Pandey <skpgkp2@gmail.com>2021-12-29 11:37:55 -0800
commitaa1809a1dfde88e5df73edba14b30e488b267343 (patch)
treee22646d81ab1bd03aa0b3295aeba2569b6f3a5c5
parent76ddc74e86f7bc36468736dd22c4c29e39cd62d8 (diff)
downloadglibc-aa1809a1dfde88e5df73edba14b30e488b267343.tar.xz
glibc-aa1809a1dfde88e5df73edba14b30e488b267343.zip
x86-64: Add vector sinh/sinhf implementation to libmvec
Implement vectorized sinh/sinhf containing SSE, AVX, AVX2 and AVX512 versions for libmvec as per vector ABI. It also contains accuracy and ABI tests for vector sinh/sinhf with regenerated ulps. Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
-rw-r--r--bits/libm-simd-decl-stubs.h11
-rw-r--r--math/bits/mathcalls.h2
-rw-r--r--sysdeps/unix/sysv/linux/x86_64/libmvec.abilist8
-rw-r--r--sysdeps/x86/fpu/bits/math-vector.h4
-rw-r--r--sysdeps/x86/fpu/finclude/math-vector-fortran.h4
-rw-r--r--sysdeps/x86_64/fpu/Makeconfig1
-rw-r--r--sysdeps/x86_64/fpu/Versions2
-rw-r--r--sysdeps/x86_64/fpu/libm-test-ulps20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core-sse2.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core.c27
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core_sse4.S456
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_sinh4_core-sse.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_sinh4_core.c27
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_sinh4_core_avx2.S470
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_sinh8_core-avx2.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_sinh8_core.c27
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_sinh8_core_avx512.S461
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_sinhf16_core-avx2.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_sinhf16_core.c28
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_sinhf16_core_avx512.S318
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_sinhf4_core-sse2.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_sinhf4_core.c28
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_sinhf4_core_sse4.S308
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_sinhf8_core-sse.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_sinhf8_core.c28
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_sinhf8_core_avx2.S309
-rw-r--r--sysdeps/x86_64/fpu/svml_d_sinh2_core.S29
-rw-r--r--sysdeps/x86_64/fpu/svml_d_sinh4_core.S29
-rw-r--r--sysdeps/x86_64/fpu/svml_d_sinh4_core_avx.S25
-rw-r--r--sysdeps/x86_64/fpu/svml_d_sinh8_core.S25
-rw-r--r--sysdeps/x86_64/fpu/svml_s_sinhf16_core.S25
-rw-r--r--sysdeps/x86_64/fpu/svml_s_sinhf4_core.S29
-rw-r--r--sysdeps/x86_64/fpu/svml_s_sinhf8_core.S29
-rw-r--r--sysdeps/x86_64/fpu/svml_s_sinhf8_core_avx.S25
-rw-r--r--sysdeps/x86_64/fpu/test-double-libmvec-sinh-avx.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-libmvec-sinh-avx2.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-libmvec-sinh-avx512f.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-libmvec-sinh.c3
-rw-r--r--sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-libmvec-sinhf-avx.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-libmvec-sinhf-avx2.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-libmvec-sinhf-avx512f.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-libmvec-sinhf.c3
-rw-r--r--sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c1
50 files changed, 2894 insertions, 1 deletions
diff --git a/bits/libm-simd-decl-stubs.h b/bits/libm-simd-decl-stubs.h
index 28dc4a82c5..6347320521 100644
--- a/bits/libm-simd-decl-stubs.h
+++ b/bits/libm-simd-decl-stubs.h
@@ -186,4 +186,15 @@
#define __DECL_SIMD_expm1f32x
#define __DECL_SIMD_expm1f64x
#define __DECL_SIMD_expm1f128x
+
+#define __DECL_SIMD_sinh
+#define __DECL_SIMD_sinhf
+#define __DECL_SIMD_sinhl
+#define __DECL_SIMD_sinhf16
+#define __DECL_SIMD_sinhf32
+#define __DECL_SIMD_sinhf64
+#define __DECL_SIMD_sinhf128
+#define __DECL_SIMD_sinhf32x
+#define __DECL_SIMD_sinhf64x
+#define __DECL_SIMD_sinhf128x
#endif
diff --git a/math/bits/mathcalls.h b/math/bits/mathcalls.h
index c57adc8ace..673b3a93ba 100644
--- a/math/bits/mathcalls.h
+++ b/math/bits/mathcalls.h
@@ -70,7 +70,7 @@ __MATHCALL (tan,, (_Mdouble_ __x));
/* Hyperbolic cosine of X. */
__MATHCALL_VEC (cosh,, (_Mdouble_ __x));
/* Hyperbolic sine of X. */
-__MATHCALL (sinh,, (_Mdouble_ __x));
+__MATHCALL_VEC (sinh,, (_Mdouble_ __x));
/* Hyperbolic tangent of X. */
__MATHCALL (tanh,, (_Mdouble_ __x));
diff --git a/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist b/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist
index c9d3213bd3..f9d7b085ab 100644
--- a/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist
@@ -53,6 +53,7 @@ GLIBC_2.35 _ZGVbN2v_cosh F
GLIBC_2.35 _ZGVbN2v_exp10 F
GLIBC_2.35 _ZGVbN2v_exp2 F
GLIBC_2.35 _ZGVbN2v_expm1 F
+GLIBC_2.35 _ZGVbN2v_sinh F
GLIBC_2.35 _ZGVbN2vv_hypot F
GLIBC_2.35 _ZGVbN4v_acosf F
GLIBC_2.35 _ZGVbN4v_asinf F
@@ -61,6 +62,7 @@ GLIBC_2.35 _ZGVbN4v_coshf F
GLIBC_2.35 _ZGVbN4v_exp10f F
GLIBC_2.35 _ZGVbN4v_exp2f F
GLIBC_2.35 _ZGVbN4v_expm1f F
+GLIBC_2.35 _ZGVbN4v_sinhf F
GLIBC_2.35 _ZGVbN4vv_hypotf F
GLIBC_2.35 _ZGVcN4v_acos F
GLIBC_2.35 _ZGVcN4v_asin F
@@ -69,6 +71,7 @@ GLIBC_2.35 _ZGVcN4v_cosh F
GLIBC_2.35 _ZGVcN4v_exp10 F
GLIBC_2.35 _ZGVcN4v_exp2 F
GLIBC_2.35 _ZGVcN4v_expm1 F
+GLIBC_2.35 _ZGVcN4v_sinh F
GLIBC_2.35 _ZGVcN4vv_hypot F
GLIBC_2.35 _ZGVcN8v_acosf F
GLIBC_2.35 _ZGVcN8v_asinf F
@@ -77,6 +80,7 @@ GLIBC_2.35 _ZGVcN8v_coshf F
GLIBC_2.35 _ZGVcN8v_exp10f F
GLIBC_2.35 _ZGVcN8v_exp2f F
GLIBC_2.35 _ZGVcN8v_expm1f F
+GLIBC_2.35 _ZGVcN8v_sinhf F
GLIBC_2.35 _ZGVcN8vv_hypotf F
GLIBC_2.35 _ZGVdN4v_acos F
GLIBC_2.35 _ZGVdN4v_asin F
@@ -85,6 +89,7 @@ GLIBC_2.35 _ZGVdN4v_cosh F
GLIBC_2.35 _ZGVdN4v_exp10 F
GLIBC_2.35 _ZGVdN4v_exp2 F
GLIBC_2.35 _ZGVdN4v_expm1 F
+GLIBC_2.35 _ZGVdN4v_sinh F
GLIBC_2.35 _ZGVdN4vv_hypot F
GLIBC_2.35 _ZGVdN8v_acosf F
GLIBC_2.35 _ZGVdN8v_asinf F
@@ -93,6 +98,7 @@ GLIBC_2.35 _ZGVdN8v_coshf F
GLIBC_2.35 _ZGVdN8v_exp10f F
GLIBC_2.35 _ZGVdN8v_exp2f F
GLIBC_2.35 _ZGVdN8v_expm1f F
+GLIBC_2.35 _ZGVdN8v_sinhf F
GLIBC_2.35 _ZGVdN8vv_hypotf F
GLIBC_2.35 _ZGVeN16v_acosf F
GLIBC_2.35 _ZGVeN16v_asinf F
@@ -101,6 +107,7 @@ GLIBC_2.35 _ZGVeN16v_coshf F
GLIBC_2.35 _ZGVeN16v_exp10f F
GLIBC_2.35 _ZGVeN16v_exp2f F
GLIBC_2.35 _ZGVeN16v_expm1f F
+GLIBC_2.35 _ZGVeN16v_sinhf F
GLIBC_2.35 _ZGVeN16vv_hypotf F
GLIBC_2.35 _ZGVeN8v_acos F
GLIBC_2.35 _ZGVeN8v_asin F
@@ -109,4 +116,5 @@ GLIBC_2.35 _ZGVeN8v_cosh F
GLIBC_2.35 _ZGVeN8v_exp10 F
GLIBC_2.35 _ZGVeN8v_exp2 F
GLIBC_2.35 _ZGVeN8v_expm1 F
+GLIBC_2.35 _ZGVeN8v_sinh F
GLIBC_2.35 _ZGVeN8vv_hypot F
diff --git a/sysdeps/x86/fpu/bits/math-vector.h b/sysdeps/x86/fpu/bits/math-vector.h
index e2f98e176f..51a41cfebc 100644
--- a/sysdeps/x86/fpu/bits/math-vector.h
+++ b/sysdeps/x86/fpu/bits/math-vector.h
@@ -90,6 +90,10 @@
# define __DECL_SIMD_expm1 __DECL_SIMD_x86_64
# undef __DECL_SIMD_expm1f
# define __DECL_SIMD_expm1f __DECL_SIMD_x86_64
+# undef __DECL_SIMD_sinh
+# define __DECL_SIMD_sinh __DECL_SIMD_x86_64
+# undef __DECL_SIMD_sinhf
+# define __DECL_SIMD_sinhf __DECL_SIMD_x86_64
# endif
#endif
diff --git a/sysdeps/x86/fpu/finclude/math-vector-fortran.h b/sysdeps/x86/fpu/finclude/math-vector-fortran.h
index 43233059f6..91e9b4fc83 100644
--- a/sysdeps/x86/fpu/finclude/math-vector-fortran.h
+++ b/sysdeps/x86/fpu/finclude/math-vector-fortran.h
@@ -44,6 +44,8 @@
!GCC$ builtin (coshf) attributes simd (notinbranch) if('x86_64')
!GCC$ builtin (expm1) attributes simd (notinbranch) if('x86_64')
!GCC$ builtin (expm1f) attributes simd (notinbranch) if('x86_64')
+!GCC$ builtin (sinh) attributes simd (notinbranch) if('x86_64')
+!GCC$ builtin (sinhf) attributes simd (notinbranch) if('x86_64')
!GCC$ builtin (cos) attributes simd (notinbranch) if('x32')
!GCC$ builtin (cosf) attributes simd (notinbranch) if('x32')
@@ -73,3 +75,5 @@
!GCC$ builtin (coshf) attributes simd (notinbranch) if('x32')
!GCC$ builtin (expm1) attributes simd (notinbranch) if('x32')
!GCC$ builtin (expm1f) attributes simd (notinbranch) if('x32')
+!GCC$ builtin (sinh) attributes simd (notinbranch) if('x32')
+!GCC$ builtin (sinhf) attributes simd (notinbranch) if('x32')
diff --git a/sysdeps/x86_64/fpu/Makeconfig b/sysdeps/x86_64/fpu/Makeconfig
index 8de8214971..81e9fc95b2 100644
--- a/sysdeps/x86_64/fpu/Makeconfig
+++ b/sysdeps/x86_64/fpu/Makeconfig
@@ -36,6 +36,7 @@ libmvec-funcs = \
pow \
sin \
sincos \
+ sinh \
# Define libmvec function for benchtests directory.
libmvec-bench-funcs = \
diff --git a/sysdeps/x86_64/fpu/Versions b/sysdeps/x86_64/fpu/Versions
index 58debb2dbe..2710446d12 100644
--- a/sysdeps/x86_64/fpu/Versions
+++ b/sysdeps/x86_64/fpu/Versions
@@ -21,6 +21,7 @@ libmvec {
_ZGVbN2v_exp10; _ZGVcN4v_exp10; _ZGVdN4v_exp10; _ZGVeN8v_exp10;
_ZGVbN2v_exp2; _ZGVcN4v_exp2; _ZGVdN4v_exp2; _ZGVeN8v_exp2;
_ZGVbN2v_expm1; _ZGVcN4v_expm1; _ZGVdN4v_expm1; _ZGVeN8v_expm1;
+ _ZGVbN2v_sinh; _ZGVcN4v_sinh; _ZGVdN4v_sinh; _ZGVeN8v_sinh;
_ZGVbN2vv_hypot; _ZGVcN4vv_hypot; _ZGVdN4vv_hypot; _ZGVeN8vv_hypot;
_ZGVbN4v_acosf; _ZGVcN8v_acosf; _ZGVdN8v_acosf; _ZGVeN16v_acosf;
_ZGVbN4v_asinf; _ZGVcN8v_asinf; _ZGVdN8v_asinf; _ZGVeN16v_asinf;
@@ -29,6 +30,7 @@ libmvec {
_ZGVbN4v_exp10f; _ZGVcN8v_exp10f; _ZGVdN8v_exp10f; _ZGVeN16v_exp10f;
_ZGVbN4v_exp2f; _ZGVcN8v_exp2f; _ZGVdN8v_exp2f; _ZGVeN16v_exp2f;
_ZGVbN4v_expm1f; _ZGVcN8v_expm1f; _ZGVdN8v_expm1f; _ZGVeN16v_expm1f;
+ _ZGVbN4v_sinhf; _ZGVcN8v_sinhf; _ZGVdN8v_sinhf; _ZGVeN16v_sinhf;
_ZGVbN4vv_hypotf; _ZGVcN8vv_hypotf; _ZGVdN8vv_hypotf; _ZGVeN16vv_hypotf;
}
}
diff --git a/sysdeps/x86_64/fpu/libm-test-ulps b/sysdeps/x86_64/fpu/libm-test-ulps
index f05ece8c8a..f4b313119d 100644
--- a/sysdeps/x86_64/fpu/libm-test-ulps
+++ b/sysdeps/x86_64/fpu/libm-test-ulps
@@ -1840,6 +1840,26 @@ float: 3
float128: 4
ldouble: 5
+Function: "sinh_vlen16":
+float: 1
+
+Function: "sinh_vlen2":
+double: 2
+
+Function: "sinh_vlen4":
+double: 2
+float: 1
+
+Function: "sinh_vlen4_avx2":
+double: 2
+
+Function: "sinh_vlen8":
+double: 2
+float: 1
+
+Function: "sinh_vlen8_avx2":
+float: 1
+
Function: "tan":
float: 1
float128: 1
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core-sse2.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core-sse2.S
new file mode 100644
index 0000000000..ca12ad6678
--- /dev/null
+++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core-sse2.S
@@ -0,0 +1,20 @@
+/* SSE2 version of vectorized sinh, vector length is 2.
+ Copyright (C) 2021 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define _ZGVbN2v_sinh _ZGVbN2v_sinh_sse2
+#include "../svml_d_sinh2_core.S"
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core.c b/sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core.c
new file mode 100644
index 0000000000..c0344b2902
--- /dev/null
+++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core.c
@@ -0,0 +1,27 @@
+/* Multiple versions of vectorized sinh, vector length is 2.
+ Copyright (C) 2021 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define SYMBOL_NAME _ZGVbN2v_sinh
+#include "ifunc-mathvec-sse4_1.h"
+
+libc_ifunc_redirected (REDIRECT_NAME, SYMBOL_NAME, IFUNC_SELECTOR ());
+
+#ifdef SHARED
+__hidden_ver1 (_ZGVbN2v_sinh, __GI__ZGVbN2v_sinh, __redirect__ZGVbN2v_sinh)
+ __attribute__ ((visibility ("hidden")));
+#endif
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core_sse4.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core_sse4.S
new file mode 100644
index 0000000000..80d19e9dba
--- /dev/null
+++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sinh2_core_sse4.S
@@ -0,0 +1,456 @@
+/* Function sinh vectorized with SSE4.
+ Copyright (C) 2021 Fre