diff options
| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-03-31 08:00:38 -0500 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-03-31 08:00:38 -0500 |
| commit | 757d9dd5c3efa56fac75965abc014faaae7b7895 (patch) | |
| tree | ce9ba1eeb3c3bb42716f669d9117ac5068e1663b /ChangeLog | |
| parent | 47c5adebd2c864a098c3af66e61e1147dc3cf0b4 (diff) | |
| download | glibc-757d9dd5c3efa56fac75965abc014faaae7b7895.tar.xz glibc-757d9dd5c3efa56fac75965abc014faaae7b7895.zip | |
PowerPC: Fix little endian enconding for mfvsrd
This patch fixes the MFVSRD_R3_V1 macro that encodes 'mfvsrd r3,vs1'
(to support old binutils) for little endian.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 13 |
1 files changed, 13 insertions, 0 deletions
@@ -1,3 +1,16 @@ +2014-03-31 Adhemerval Zanella <azanella@linux.vnet.ibm.com> + + * sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S (MFVSRD_R3_V1): + Encode instruction correctly in little endian. + * sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S (MFVSRD_R3_V1): + Likewise. + * sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S (MFVSRD_R3_V1): + Likewise. + * sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S (MFVSRD_R3_V1): + Likewise. + * sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S (MFVSRD_R3_V1): + Likewise. + 2014-03-31 Joseph Myers <joseph@codesourcery.com> [BZ #9894] |