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authorH.J. Lu <hjl.tools@gmail.com>2015-03-31 13:17:51 -0700
committerH.J. Lu <hjl.tools@gmail.com>2015-03-31 13:18:10 -0700
commita3d9ab5070b56b49aa91be2887fa5b118012b2cd (patch)
tree4352143efb08c51ec9cb480489e847de724afb06 /ChangeLog
parent83569fb894050db7430047da2219ca50c68f882a (diff)
downloadglibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.tar.xz
glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.zip
Limit threads sharing L2 cache to 2 for SLM/KNL
Silvermont and Knights Landing have a modular system design with two cores sharing an L2 cache. If more than 2 cores are detected to shared L2 cache, it should be adjusted for Silvermont and Knights Landing. [BZ #18185] * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads sharing L2 cache to 2 for Silvermont/Knights Landing.
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2015-03-31 H.J. Lu <hongjiu.lu@intel.com>
+ [BZ #18185]
+ * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads
+ sharing L2 cache to 2 for Silvermont/Knights Landing.
+
+2015-03-31 H.J. Lu <hongjiu.lu@intel.com>
+
[BZ #17711]
* config.make.in (have-protected-data): New.
* configure.ac: Check linker support for protected data symbol.