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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-10-05 17:10:52 +0100 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-10-23 15:00:45 +0100 |
| commit | 31aaf6fed986fade042f9ffe7535d8b3f2c173a2 (patch) | |
| tree | 5417d6dffd8eefa74a1506a792ed40330205ce31 /sysdeps/aarch64/fpu/Versions | |
| parent | 067a34156c19fb3c53824e37d70820c0ce5b87b2 (diff) | |
| download | glibc-31aaf6fed986fade042f9ffe7535d8b3f2c173a2.tar.xz glibc-31aaf6fed986fade042f9ffe7535d8b3f2c173a2.zip | |
aarch64: Add vector implementations of exp10 routines
Double-precision routines either reuse the exp table (AdvSIMD) or use
SVE FEXPA intruction.
Diffstat (limited to 'sysdeps/aarch64/fpu/Versions')
| -rw-r--r-- | sysdeps/aarch64/fpu/Versions | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions index 358efed5ee..eb5ad50017 100644 --- a/sysdeps/aarch64/fpu/Versions +++ b/sysdeps/aarch64/fpu/Versions @@ -18,6 +18,10 @@ libmvec { _ZGVsMxv_sinf; } GLIBC_2.39 { + _ZGVnN4v_exp10f; + _ZGVnN2v_exp10; + _ZGVsMxv_exp10f; + _ZGVsMxv_exp10; _ZGVnN4v_exp2f; _ZGVnN2v_exp2; _ZGVsMxv_exp2f; |