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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2024-02-20 16:59:41 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2024-04-04 10:33:02 +0100 |
| commit | 81406ea3c5b5ad19e307302c13dd642785b47948 (patch) | |
| tree | 41d3ff76044aaa82af028c67c25b39aaad8ace3a /sysdeps/aarch64/fpu/bits/math-vector.h | |
| parent | b09fee1d21650428a6a3335408a46ebe1165d30d (diff) | |
| download | glibc-81406ea3c5b5ad19e307302c13dd642785b47948.tar.xz glibc-81406ea3c5b5ad19e307302c13dd642785b47948.zip | |
aarch64/fpu: Add vector variants of asinh
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'sysdeps/aarch64/fpu/bits/math-vector.h')
| -rw-r--r-- | sysdeps/aarch64/fpu/bits/math-vector.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h index 841330956c..eb2af35b27 100644 --- a/sysdeps/aarch64/fpu/bits/math-vector.h +++ b/sysdeps/aarch64/fpu/bits/math-vector.h @@ -41,6 +41,10 @@ # define __DECL_SIMD_asin __DECL_SIMD_aarch64 # undef __DECL_SIMD_asinf # define __DECL_SIMD_asinf __DECL_SIMD_aarch64 +# undef __DECL_SIMD_asinh +# define __DECL_SIMD_asinh __DECL_SIMD_aarch64 +# undef __DECL_SIMD_asinhf +# define __DECL_SIMD_asinhf __DECL_SIMD_aarch64 # undef __DECL_SIMD_atan # define __DECL_SIMD_atan __DECL_SIMD_aarch64 # undef __DECL_SIMD_atanf @@ -131,6 +135,7 @@ __vpcs __f32x4_t _ZGVnN4vv_atan2f (__f32x4_t, __f32x4_t); __vpcs __f32x4_t _ZGVnN4v_acosf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_acoshf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_asinf (__f32x4_t); +__vpcs __f32x4_t _ZGVnN4v_asinhf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_atanf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_coshf (__f32x4_t); @@ -150,6 +155,7 @@ __vpcs __f64x2_t _ZGVnN2vv_atan2 (__f64x2_t, __f64x2_t); __vpcs __f64x2_t _ZGVnN2v_acos (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_acosh (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_asin (__f64x2_t); +__vpcs __f64x2_t _ZGVnN2v_asinh (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_atan (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_cosh (__f64x2_t); @@ -174,6 +180,7 @@ __sv_f32_t _ZGVsMxvv_atan2f (__sv_f32_t, __sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_acosf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_acoshf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_asinf (__sv_f32_t, __sv_bool_t); +__sv_f32_t _ZGVsMxv_asinhf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_atanf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_coshf (__sv_f32_t, __sv_bool_t); @@ -193,6 +200,7 @@ __sv_f64_t _ZGVsMxvv_atan2 (__sv_f64_t, __sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_acos (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_acosh (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_asin (__sv_f64_t, __sv_bool_t); +__sv_f64_t _ZGVsMxv_asinh (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_atan (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_cosh (__sv_f64_t, __sv_bool_t); |