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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2024-02-20 16:59:45 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2024-04-04 10:33:24 +0100 |
| commit | 87cb1dfcd6d1acbcd695279d7abd9163a0cc64fc (patch) | |
| tree | 4730b4daebe2d00354d27a2e3852309660e60a45 /sysdeps/aarch64/fpu/bits | |
| parent | 3d3a4fb8e4fe854a0bbb3df9c26ba482c10a7e22 (diff) | |
| download | glibc-87cb1dfcd6d1acbcd695279d7abd9163a0cc64fc.tar.xz glibc-87cb1dfcd6d1acbcd695279d7abd9163a0cc64fc.zip | |
aarch64/fpu: Add vector variants of erfc
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'sysdeps/aarch64/fpu/bits')
| -rw-r--r-- | sysdeps/aarch64/fpu/bits/math-vector.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h index 585e022082..e29b2d1c09 100644 --- a/sysdeps/aarch64/fpu/bits/math-vector.h +++ b/sysdeps/aarch64/fpu/bits/math-vector.h @@ -69,6 +69,10 @@ # define __DECL_SIMD_erf __DECL_SIMD_aarch64 # undef __DECL_SIMD_erff # define __DECL_SIMD_erff __DECL_SIMD_aarch64 +# undef __DECL_SIMD_erfc +# define __DECL_SIMD_erfc __DECL_SIMD_aarch64 +# undef __DECL_SIMD_erfcf +# define __DECL_SIMD_erfcf __DECL_SIMD_aarch64 # undef __DECL_SIMD_exp # define __DECL_SIMD_exp __DECL_SIMD_aarch64 # undef __DECL_SIMD_expf @@ -153,6 +157,7 @@ __vpcs __f32x4_t _ZGVnN4v_atanhf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_coshf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_erff (__f32x4_t); +__vpcs __f32x4_t _ZGVnN4v_erfcf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_expf (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_exp10f (__f32x4_t); __vpcs __f32x4_t _ZGVnN4v_exp2f (__f32x4_t); @@ -176,6 +181,7 @@ __vpcs __f64x2_t _ZGVnN2v_atanh (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_cosh (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_erf (__f64x2_t); +__vpcs __f64x2_t _ZGVnN2v_erfc (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_exp (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_exp10 (__f64x2_t); __vpcs __f64x2_t _ZGVnN2v_exp2 (__f64x2_t); @@ -204,6 +210,7 @@ __sv_f32_t _ZGVsMxv_atanhf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_coshf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_erff (__sv_f32_t, __sv_bool_t); +__sv_f32_t _ZGVsMxv_erfcf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_expf (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_exp10f (__sv_f32_t, __sv_bool_t); __sv_f32_t _ZGVsMxv_exp2f (__sv_f32_t, __sv_bool_t); @@ -227,6 +234,7 @@ __sv_f64_t _ZGVsMxv_atanh (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_cosh (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_erf (__sv_f64_t, __sv_bool_t); +__sv_f64_t _ZGVsMxv_erfc (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_exp (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_exp10 (__sv_f64_t, __sv_bool_t); __sv_f64_t _ZGVsMxv_exp2 (__sv_f64_t, __sv_bool_t); |