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| author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2025-01-02 16:12:34 -0300 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2025-01-13 10:17:38 -0300 |
| commit | 6c575d835edf166c16695e47732b175abf6f99ef (patch) | |
| tree | aba67ac7c17354a236bc98ddf62ff11d1a89aa51 /sysdeps/aarch64 | |
| parent | e9f16cb6d187df00e7f28992436339d343e00760 (diff) | |
| download | glibc-6c575d835edf166c16695e47732b175abf6f99ef.tar.xz glibc-6c575d835edf166c16695e47732b175abf6f99ef.zip | |
aarch64: Use 64-bit variable to access the special registers
clang issues:
error: value size does not match register size specified by the
constraint and modifier [-Werror,-Wasm-operand-widths]
while tryng to use 32 bit variables with 'mrs' to get/set the
fpsr, dczid_el0, and ctr.
Diffstat (limited to 'sysdeps/aarch64')
| -rw-r--r-- | sysdeps/aarch64/fpu/fpu_control.h | 36 | ||||
| -rw-r--r-- | sysdeps/aarch64/fpu/fraiseexcpt.c | 3 | ||||
| -rw-r--r-- | sysdeps/aarch64/sfp-machine.h | 2 |
3 files changed, 28 insertions, 13 deletions
diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h index 5df6da3ffc..a93dbf5efa 100644 --- a/sysdeps/aarch64/fpu/fpu_control.h +++ b/sysdeps/aarch64/fpu/fpu_control.h @@ -29,17 +29,31 @@ # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ()) # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr) #else -# define _FPU_GETCW(fpcr) \ - __asm__ __volatile__ ("mrs %0, fpcr" : "=r" (fpcr)) - -# define _FPU_SETCW(fpcr) \ - __asm__ __volatile__ ("msr fpcr, %0" : : "r" (fpcr)) - -# define _FPU_GETFPSR(fpsr) \ - __asm__ __volatile__ ("mrs %0, fpsr" : "=r" (fpsr)) - -# define _FPU_SETFPSR(fpsr) \ - __asm__ __volatile__ ("msr fpsr, %0" : : "r" (fpsr)) +# define _FPU_GETCW(fpcr) \ + ({ \ + __uint64_t __fpcr; \ + __asm__ __volatile__ ("mrs %0, fpcr" : "=r" (__fpcr)); \ + fpcr = __fpcr; \ + }) + +# define _FPU_SETCW(fpcr) \ + ({ \ + __uint64_t __fpcr = fpcr; \ + __asm__ __volatile__ ("msr fpcr, %0" : : "r" (__fpcr)); \ + }) + +# define _FPU_GETFPSR(fpsr) \ + ({ \ + __uint64_t __fpsr; \ + __asm__ __volatile__ ("mrs %0, fpsr" : "=r" (__fpsr)); \ + fpsr = __fpsr; \ + }) + +# define _FPU_SETFPSR(fpsr) \ + ({ \ + __uint64_t __fpsr = fpsr; \ + __asm__ __volatile__ ("msr fpsr, %0" : : "r" (__fpsr)); \ + }) #endif /* Reserved bits should be preserved when modifying register diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c index bf5862a56e..518a6eb321 100644 --- a/sysdeps/aarch64/fpu/fraiseexcpt.c +++ b/sysdeps/aarch64/fpu/fraiseexcpt.c @@ -19,11 +19,12 @@ #include <fenv.h> #include <fpu_control.h> #include <float.h> +#include <stdint.h> int __feraiseexcept (int excepts) { - int fpsr; + uint64_t fpsr; const float fp_zero = 0.0; const float fp_one = 1.0; const float fp_max = FLT_MAX; diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h index a9ecdbf961..b41a9462df 100644 --- a/sysdeps/aarch64/sfp-machine.h +++ b/sysdeps/aarch64/sfp-machine.h @@ -74,7 +74,7 @@ do { \ const float fp_1e32 = 1.0e32f; \ const float fp_zero = 0.0; \ const float fp_one = 1.0; \ - unsigned fpsr; \ + uint64_t fpsr; \ if (_fex & FP_EX_INVALID) \ { \ __asm__ __volatile__ ("fdiv\ts0, %s0, %s0" \ |