Relocate alpha from ports to libc

Also fixed the following whitespace nits to satisfy the push:

sysdeps/alpha/alphaev6/memset.S:142: space before tab in indent.
sysdeps/alpha/configure:1: new blank line at EOF.
sysdeps/alpha/fpu/e_sqrt.c:126: space before tab in indent.
sysdeps/alpha/preconfigure:1: new blank line at EOF.
sysdeps/unix/sysv/linux/alpha/syscalls.list:1: new blank line at EOF.

77 files changed, 22215 insertions, 0 deletions

diff --git a/sysdeps/alpha/fpu/Versions b/sysdeps/alpha/fpu/Versions
new file mode 100644
index 0000000000..c9b0e03a91
--- /dev/null
+++ b/sysdeps/alpha/fpu/Versions
@@ -0,0 +1,23 @@
+libc {
+  GLIBC_2.0 {
+    # functions used in other libraries
+    __ieee_get_fp_control; __ieee_set_fp_control;
+  }
+}
+libm {
+  GLIBC_2.3.4 {
+    # functions implementing old complex float abi
+    __c1_cabsf; __c1_cacosf; __c1_cacoshf; __c1_cargf; __c1_casinf;
+    __c1_casinhf; __c1_catanf; __c1_catanhf; __c1_ccosf; __c1_ccoshf;
+    __c1_cexpf; __c1_cimagf; __c1_clog10f; __c1_clogf; __c1_conjf;
+    __c1_cpowf; __c1_cprojf; __c1_crealf; __c1_csinf; __c1_csinhf;
+    __c1_csqrtf; __c1_ctanf; __c1_ctanhf;
+
+    # functions implementing new complex float abi
+    cabsf; cacosf; cacoshf; cargf; casinf;
+    casinhf; catanf; catanhf; ccosf; ccoshf;
+    cexpf; cimagf; clog10f; clogf; conjf;
+    cpowf; cprojf; crealf; csinf; csinhf;
+    csqrtf; ctanf; ctanhf;
+  }
+}
diff --git a/sysdeps/alpha/fpu/bits/fenv.h b/sysdeps/alpha/fpu/bits/fenv.h
new file mode 100644
index 0000000000..4dba9b59a0
--- /dev/null
+++ b/sysdeps/alpha/fpu/bits/fenv.h
@@ -0,0 +1,133 @@
+/* Copyright (C) 1997-2014 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _FENV_H
+# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
+#endif
+
+
+/* Define the bits representing the exception.
+
+   Note that these are the bit positions as defined by the OSF/1
+   ieee_{get,set}_control_word interface and not by the hardware fpcr.
+
+   See the Alpha Architecture Handbook section 4.7.7.3 for details,
+   but in summary, trap shadows mean the hardware register can acquire
+   extra exception bits so for proper IEEE support the tracking has to
+   be done in software -- in this case with kernel support.
+
+   As to why the system call interface isn't in the same format as
+   the hardware register, only those crazy folks at DEC can tell you.  */
+
+enum
+  {
+#ifdef __USE_GNU
+    FE_DENORMAL =
+#define FE_DENORMAL	(1 << 22)
+      FE_DENORMAL,
+#endif
+
+    FE_INEXACT =
+#define FE_INEXACT	(1 << 21)
+      FE_INEXACT,
+
+    FE_UNDERFLOW =
+#define FE_UNDERFLOW	(1 << 20)
+      FE_UNDERFLOW,
+
+    FE_OVERFLOW =
+#define FE_OVERFLOW	(1 << 19)
+      FE_OVERFLOW,
+
+    FE_DIVBYZERO =
+#define FE_DIVBYZERO	(1 << 18)
+      FE_DIVBYZERO,
+
+    FE_INVALID =
+#define FE_INVALID	(1 << 17)
+      FE_INVALID,
+
+    FE_ALL_EXCEPT =
+#define FE_ALL_EXCEPT	(0x3f << 17)
+      FE_ALL_EXCEPT
+  };
+
+/* Alpha chips support all four defined rouding modes.
+
+   Note that code must be compiled to use dynamic rounding (/d) instructions
+   to see these changes.  For gcc this is -mfp-rounding-mode=d; for DEC cc
+   this is -fprm d.  The default for both is static rounding to nearest.
+
+   These are shifted down 58 bits from the hardware fpcr because the
+   functions are declared to take integers.  */
+
+enum
+  {
+    FE_TOWARDZERO =
+#define FE_TOWARDZERO	0
+      FE_TOWARDZERO,
+
+    FE_DOWNWARD =
+#define FE_DOWNWARD	1
+      FE_DOWNWARD,