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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-09-18 07:55:14 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2021-01-14 11:38:45 -0800 |
| commit | 2d651eb9265d1366d7b9e881bfddd46db9c1ecc4 (patch) | |
| tree | e7ab45e6e14b7be7729b8ae06aa911f97d446d37 /sysdeps/x86/include | |
| parent | d18f59bf9223e9342be16baa2411ef3acc3f7ea4 (diff) | |
| download | glibc-2d651eb9265d1366d7b9e881bfddd46db9c1ecc4.tar.xz glibc-2d651eb9265d1366d7b9e881bfddd46db9c1ecc4.zip | |
x86: Move x86 processor cache info to cpu_features
1. Move x86 processor cache info to _dl_x86_cpu_features in ld.so.
2. Update tunable bounds with TUNABLE_SET_WITH_BOUNDS.
3. Move x86 cache info initialization to dl-cacheinfo.h and initialize
x86 cache info in init_cpu_features ().
4. Put x86 cache info for libc in cacheinfo.h, which is included in
libc-start.c in libc.a and is included in cacheinfo.c in libc.so.
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Diffstat (limited to 'sysdeps/x86/include')
| -rw-r--r-- | sysdeps/x86/include/cpu-features.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index 99e7ee08cf..50cb5a15f5 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -149,6 +149,28 @@ struct cpu_features unsigned long int rep_movsb_threshold; /* Threshold to use "rep stosb". */ unsigned long int rep_stosb_threshold; + /* _SC_LEVEL1_ICACHE_SIZE. */ + unsigned long int level1_icache_size; + /* _SC_LEVEL1_DCACHE_SIZE. */ + unsigned long int level1_dcache_size; + /* _SC_LEVEL1_DCACHE_ASSOC. */ + unsigned long int level1_dcache_assoc; + /* _SC_LEVEL1_DCACHE_LINESIZE. */ + unsigned long int level1_dcache_linesize; + /* _SC_LEVEL2_CACHE_ASSOC. */ + unsigned long int level2_cache_size; + /* _SC_LEVEL2_DCACHE_ASSOC. */ + unsigned long int level2_cache_assoc; + /* _SC_LEVEL2_CACHE_LINESIZE. */ + unsigned long int level2_cache_linesize; + /* /_SC_LEVEL3_CACHE_SIZE. */ + unsigned long int level3_cache_size; + /* _SC_LEVEL3_CACHE_ASSOC. */ + unsigned long int level3_cache_assoc; + /* _SC_LEVEL3_CACHE_LINESIZE. */ + unsigned long int level3_cache_linesize; + /* /_SC_LEVEL4_CACHE_SIZE. */ + unsigned long int level4_cache_size; }; #if defined (_LIBC) && !IS_IN (nonlib) |