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| author | H.J. Lu <hjl.tools@gmail.com> | 2023-12-29 08:43:52 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2024-01-01 05:22:48 -0800 |
| commit | d360dcc001cb12504cd3e8dbddee20df6bebb0f8 (patch) | |
| tree | 85424ab05ed848c3e004bb938e4e7820f9c77e1c /sysdeps/x86/sys | |
| parent | 541641a3de8d89464151bd879552755e882c832e (diff) | |
| download | glibc-d360dcc001cb12504cd3e8dbddee20df6bebb0f8.tar.xz glibc-d360dcc001cb12504cd3e8dbddee20df6bebb0f8.zip | |
x86/cet: Check feature_1 in TCB for active IBT and SHSTK
Initially, IBT and SHSTK are marked as active when CPU supports them
and CET are enabled in glibc. They can be disabled early by tunables
before relocation. Since after relocation, GLRO(dl_x86_cpu_features)
becomes read-only, we can't update GLRO(dl_x86_cpu_features) to mark
IBT and SHSTK as inactive. Instead, check the feature_1 field in TCB
to decide if IBT and SHST are active.
Diffstat (limited to 'sysdeps/x86/sys')
| -rw-r--r-- | sysdeps/x86/sys/platform/x86.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h index 1ea2c5fc0b..89b1b16f22 100644 --- a/sysdeps/x86/sys/platform/x86.h +++ b/sysdeps/x86/sys/platform/x86.h @@ -45,6 +45,23 @@ x86_cpu_present (unsigned int __index) static __inline__ _Bool x86_cpu_active (unsigned int __index) { + if (__index == x86_cpu_IBT || __index == x86_cpu_SHSTK) + { +#ifdef __x86_64__ + unsigned int __feature_1; +# ifdef __LP64__ + __asm__ ("mov %%fs:72, %0" : "=r" (__feature_1)); +# else + __asm__ ("mov %%fs:40, %0" : "=r" (__feature_1)); +# endif + if (__index == x86_cpu_IBT) + return __feature_1 & x86_feature_1_ibt; + else + return __feature_1 & x86_feature_1_shstk; +#else + return false; +#endif + } const struct cpuid_feature *__ptr = __x86_get_cpuid_feature_leaf (__index / (8 * sizeof (unsigned int) * 4)); unsigned int __reg |