Fix misspellings in sysdeps/x86_64 -- BZ 25337.

Applying this commit results in bit-identical rebuild of libc.so.6
math/libm.so.6 elf/ld-linux-x86-64.so.2 mathvec/libmvec.so.1

Reviewed-by: Florian Weimer <fweimer@redhat.com>

35 files changed, 98 insertions, 98 deletions

diff --git a/sysdeps/x86_64/multiarch/ifunc-strcasecmp.h b/sysdeps/x86_64/multiarch/ifunc-strcasecmp.h
index 10ae5d6994..89d366b7b5 100644
--- a/sysdeps/x86_64/multiarch/ifunc-strcasecmp.h
+++ b/sysdeps/x86_64/multiarch/ifunc-strcasecmp.h
@@ -1,4 +1,4 @@
-/* Common definition for strcasecmp famly ifunc selections.
+/* Common definition for strcasecmp family ifunc selections.
    All versions must be listed in ifunc-impl-list.c.
    Copyright (C) 2017-2023 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S
index 764a419b68..35347daa05 100644
--- a/sysdeps/x86_64/multiarch/memchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memchr-evex.S
@@ -440,13 +440,13 @@ L(loop_4x_vec):
 	   ymm0-15 is used at all is because there is no EVEX encoding
 	   vpcmpeq and with vpcmpeq this loop can be performed more
 	   efficiently.  The non-vzeroupper version is safe for RTM
-	   while the vzeroupper version should be prefered if RTM are
+	   while the vzeroupper version should be preferred if RTM are
 	   not supported.   Which loop version we use is determined by
 	   USE_TERN_IN_LOOP.  */
 
 # if USE_TERN_IN_LOOP
 	/* Since vptern can only take 3x vectors fastest to do 1 vec
-	   seperately with EVEX vpcmp.  */
+	   separately with EVEX vpcmp.  */
 #  ifdef USE_AS_WMEMCHR
 	/* vptern can only accept masks for epi32/epi64 so can only save
 	   instruction using not equals mask on vptern with wmemchr.
@@ -539,7 +539,7 @@ L(last_vec_x1_novzero):
 
 # if CHAR_PER_VEC == 64
 	/* Since we can't combine the last 2x VEC when CHAR_PER_VEC ==
-	   64 it needs a seperate return label.  */
+	   64 it needs a separate return label.  */
 	.p2align 4,, 4
 L(last_vec_x2):
 L(last_vec_x2_novzero):
@@ -579,8 +579,8 @@ L(loop_vec_ret):
 	   (only if used VEX encoded loop).  */
 	COND_VZEROUPPER
 
-	/* Seperate logic for CHAR_PER_VEC == 64 vs the rest.  For
-	   CHAR_PER_VEC we test the last 2x VEC seperately, for
+	/* Separate logic for CHAR_PER_VEC == 64 vs the rest.  For
+	   CHAR_PER_VEC we test the last 2x VEC separately, for
 	   CHAR_PER_VEC <= 32 we can combine the results from the 2x
 	   VEC in a single GPR.  */
 # if CHAR_PER_VEC == 64
diff --git a/sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S b/sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S
index b81d9f7dd8..61dbfe79cf 100644
--- a/sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S
+++ b/sysdeps/x86_64/multiarch/memcmp-avx2-movbe.S
@@ -29,7 +29,7 @@
    3. Use xmm vector compare when size >= 4 bytes for memcmp or
       size >= 8 bytes for wmemcmp.
    4. Optimistically compare up to first 4 * VEC_SIZE one at a
-      to check for early mismatches. Only do this if its guranteed the
+      to check for early mismatches. Only do this if its guaranteed the
       work is not wasted.
    5. If size is 8 * VEC_SIZE or less, unroll the loop.
    6. Compare 4 * VEC_SIZE at a time with the aligned first memory
@@ -66,7 +66,7 @@
 
 /* Warning!
            wmemcmp has to use SIGNED comparison for elements.
-           memcmp has to use UNSIGNED comparison for elemnts.
+           memcmp has to use UNSIGNED comparison for elements.
 */
 
 	.section SECTION(.text),"ax",@progbits
diff --git a/sysdeps/x86_64/multiarch/memcmp-evex-movbe.S b/sysdeps/x86_64/multiarch/memcmp-evex-movbe.S
index a63db75b35..7e6fed9b63 100644
--- a/sysdeps/x86_64/multiarch/memcmp-evex-movbe.S
+++ b/sysdeps/x86_64/multiarch/memcmp-evex-movbe.S
@@ -30,7 +30,7 @@
    3. Use xmm vector compare when size >= 4 bytes for memcmp or
       size >= 8 bytes for wmemcmp.
    4. Optimistically compare up to first 4 * CHAR_PER_VEC one at a
-      to check for early mismatches. Only do this if its guranteed the
+      to check for early mismatches. Only do this if its guaranteed the
       work is not wasted.
    5. If size is 8 * VEC_SIZE or less, unroll the loop.
    6. Compare 4 * VEC_SIZE at a time with the aligned first memory
@@ -90,7 +90,7 @@ Latency:
 
 /* Warning!
            wmemcmp has to use SIGNED comparison for elements.
-           memcmp has to use UNSIGNED comparison for elemnts.
+           memcmp has to use UNSIGNED comparison for elements.
 */
 
 	.section SECTION(.text), "ax", @progbits
@@ -105,7 +105,7 @@ ENTRY_P2ALIGN (MEMCMP, 6)
 	/* Fall through for [0, VEC_SIZE] as its the hottest.  */
 	ja	L(more_1x_vec)
 
-	/* Create mask of bytes that are guranteed to be valid because
+	/* Create mask of bytes that are guaranteed to be valid because
 	   of length (edx). Using masked movs allows us to skip checks
 	   for page crosses/zero size.  */
 	mov	$-1, %VRAX
@@ -365,7 +365,7 @@ L(loop_4x_vec):
 	/* Load regardless of branch.  */
 	VMOVU	(VEC_SIZE * 2)(%rsi, %rdx), %VMM(3)
 
-	/* Seperate logic as we can only use testb for VEC_SIZE == 64.
+	/* Separate logic as we can only use testb for VEC_SIZE == 64.
 	 */
 # if VEC_SIZE == 64
 	testb	%dil, %dil
diff --git a/sysdeps/x86_64/multiarch/memcmp-sse2.S b/sysdeps/x86_64/multiarch/memcmp-sse2.S
index 305bd02920..77174e7c64 100644
--- a/sysdeps/x86_64/multiarch/memcmp-sse2.S
+++ b/sysdeps/x86_64/multiarch/memcmp-sse2.S
@@ -410,7 +410,7 @@ L(ret_nonzero_vec_start_4_5):
 	.p2align 4,, 8
 L(ret_nonzero_vec_end_1):
 	pmovmskb %xmm1, %ecx
-	/* High 16 bits of eax guranteed to be all ones. Rotate them in
+	/* High 16 bits of eax guaranteed to be all ones. Rotate them in
 	   to we can do `or + not` with just `xor`.  */
 	rorl	$16, %eax
 	xorl	%ecx, %eax
@@ -562,7 +562,7 @@ L(ret_nonzero_loop):
 	sall	$(VEC_SIZE * 1), %edx
 	leal	1(%rcx, %rdx), %edx
 	pmovmskb %xmm2, %ecx
-	/* High 16 bits of eax guranteed to be all ones. Rotate them in
+	/* High 16 bits of eax guaranteed to be all ones. Rotate them in
 	   to we can do `or + not` with just `xor`.  */
 	rorl	$16, %eax
 	xorl	%ecx, %eax
diff --git a/sysdeps/x86_64/multiarch/memcmpeq-avx2.S b/sysdeps/x86_64/multiarch/memcmpeq-avx2.S
index 4b013c5523..f6e39ca0bd 100644
--- a/sysdeps/x86_64/multiarch/memcmpeq-avx2.S
+++ b/sysdeps/x86_64/multiarch/memcmpeq-avx2.S
@@ -26,7 +26,7 @@
       and loading from either s1 or s2 would cause a page cross.
    2. Use xmm vector compare when size >= 8 bytes.
    3. Optimistically compare up to first 4 * VEC_SIZE one at a
-      to check for early mismatches. Only do this if its guranteed the
+      to check for early mismatches. Only do this if its guaranteed the
       work is not wasted.
    4. If size is 8 * VEC_SIZE or less, unroll the loop.
    5. Compare 4 * VEC_SIZE at a time with the aligned first memory
@@ -302,7 +302,7 @@ L(between_9_15):
 	movq	-8(%rsi, %rdx), %rdi
 	subq	%rdi, %rcx
 	orq	%rcx, %rax
-	/* edx is guranteed to be a non-zero int.  */
+	/* edx is guaranteed to be a non-zero int.  */
 	cmovnz	%edx, %eax
 	ret
 
diff --git a/sysdeps/x86_64/multiarch/memcmpeq-evex.S b/sysdeps/x86_64/multiarch/memcmpeq-evex.S
index 7ae3e3c8c9..3666f649cd 100644
--- a/sysdeps/x86_64/multiarch/memcmpeq-evex.S
+++ b/sysdeps/x86_64/multiarch/memcmpeq-evex.S
@@ -26,7 +26,7 @@
       and loading from either s1 or s2 would cause a page cross.
    2. Use xmm vector compare when size >= 8 bytes.
    3. Optimistically compare up to first 4 * VEC_SIZE one at a
-      to check for early mismatches. Only do this if its guranteed the
+      to check for early mismatches. Only do this if its guaranteed the
       work is not wasted.
    4. If size is 8 * VEC_SIZE or less, unroll the loop.
    5. Compare 4 * VEC_SIZE at a time with the aligned first memory
@@ -97,7 +97,7 @@ ENTRY_P2ALIGN (MEMCMPEQ, 6)
 	/* Fall through for [0, VEC_SIZE] as its the hottest.  */
 	ja	L(more_1x_vec)
 
-	/* Create mask of bytes that are guranteed to be valid because
+	/* Create mask of bytes that are guaranteed to be valid because
 	   of length (edx). Using masked movs allows us to skip checks
 	   for page crosses/zero size.  */
 	mov	$-1, %VRAX
@@ -253,7 +253,7 @@ L(loop_4x_vec):
 	   oring with VEC(4). Result is stored in VEC(4).  */
 	vpternlogd $0xf6, (VEC_SIZE * 2)(%rdx), %VMM(3), %VMM(4)
 
-	/* Seperate logic as we can only use testb for VEC_SIZE == 64.
+	/* Separate logic as we can only use testb for VEC_SIZE == 64.
 	 */
 # if VEC_SIZE == 64
 	testb	%dil, %dil
diff --git a/sysdeps/x86_64/multiarch/memmove-ssse3.S b/sysdeps/x86_64/multiarch/memmove-ssse3.S
index ded86bd1e5..460b0ec044 100644
--- a/sysdeps/x86_64/multiarch/memmove-ssse3.S
+++ b/sysdeps/x86_64/multiarch/memmove-ssse3.S
@@ -231,7 +231,7 @@ L(end_loop_fwd):
 	movups	%xmm7, 48(%r8)
 	ret
 
-	/* Extactly 64 bytes if `jmp L(end_loop_fwd)` is long encoding.
+	/* Exactly 64 bytes if `jmp L(end_loop_fwd)` is long encoding.
 	   60 bytes otherwise.  */
 # define ALIGNED_LOOP_FWD(align_by);	\
 	.p2align 6;	\
@@ -368,7 +368,7 @@ L(end_loop_bkwd):
 	ret
 
 
-	/* Extactly 64 bytes if `jmp L(end_loop_bkwd)` is long encoding.
+	/* Exactly 64 bytes if `jmp L(end_loop_bkwd)` is long encoding.
 	   60 bytes otherwise.  */
 # define ALIGNED_LOOP_BKWD(align_by);	\
 	.p2align 6;	\
diff --git a/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S
index d1b92785b0..51eb622bc8 100644
--- a/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S
+++ b/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S
@@ -445,7 +445,7 @@ L(more_8x_vec_check):
 	shrq	$63, %r8
 	/* Get 4k difference dst - src.  */
 	andl	$(PAGE_SIZE - 256), %ecx
-	/* If r8 is non-zero must do foward for correctness. Otherwise
+	/* If r8 is non-zero must do forward for correctness. Otherwise
 	   if ecx is non-zero there is 4k False Alaising so do backward
 	   copy.  */
 	addl	%r8d, %ecx
@@ -460,7 +460,7 @@ L(more_8x_vec_forward):
 	/* First vec was already loaded into VEC(0).  */
 	VMOVU	-VEC_SIZE(%rsi, %rdx), %VMM(5)
 	VMOVU	-(VEC_SIZE * 2)(%rsi, %rdx), %VMM(6)
-	/* Save begining of dst.  */
+	/* Save beginning of dst.  */
 	movq	%rdi, %rcx
 	/* Align dst to VEC_SIZE - 1.  */
 	orq	$(VEC_SIZE - 1), %rdi
@@ -517,7 +517,7 @@ L(more_8x_vec_backward):
 	/* First vec was also loaded into VEC(0).  */
 	VMOVU	VEC_SIZE(%rsi), %VMM(5)
 	VMOVU	(VEC_SIZE * 2)(%rsi), %VMM(6)
-	/* Begining of region for 4x backward copy stored in rcx.  */
+	/* Beginning of region for 4x backward copy stored in rcx.  */
 	leaq	(VEC_SIZE * -4 + -1)(%rdi, %rdx), %rcx
 	VMOVU	(VEC_SIZE * 3)(%rsi), %VMM(7)
 	VMOVU	-VEC_SIZE(%rsi, %rdx), %VMM(8)
@@ -611,7 +611,7 @@ L(movsb):
 	movq	%rdi, %r8
 # endif
 	/* If above __x86_rep_movsb_stop_threshold most likely is
-	   candidate for NT moves aswell.  */
+	   candidate for NT moves as well.  */
 	cmp	__x86_rep_movsb_stop_threshold(%rip), %RDX_LP
 	jae	L(large_memcpy_2x_check)
 # if AVOID_SHORT_DISTANCE_REP_MOVSB || ALIGN_MOVSB
diff --git a/sysdeps/x86_64/multiarch/memrchr-avx2.S b/sysdeps/x86_64/multiarch/memrchr-avx2.S
index 15c83f6a2b..409706fd8e 100644
--- a/sysdeps/x86_64/multiarch/memrchr-avx2.S
+++ b/sysdeps/x86_64/multiarch/memrchr-avx2.S
@@ -65,7 +65,7 @@ ENTRY_P2ALIGN(MEMRCHR, 6)
 
 L(ret_vec_x0_test):
 	/* If ecx is zero (no matches) lzcnt will set it 32 (VEC_SIZE) which
-	   will gurantee edx (len) is less than it.  */
+	   will guarantee edx (len) is less than it.  */
 	lzcntl	%ecx, %ecx
 
 	/* Hoist vzeroupper (not great for RTM) to save code size. This allows
@@ -233,7 +233,7 @@ L(more_4x_vec):
 	jnz	L(ret_vec_x3)
 
 	/* Check if near end before re-aligning (otherwise might do an
-	   unnecissary loop iteration).  */
+	   unnecessary loop iteration).  */
 	addq	$-(VEC_SIZE * 4), %rax
 	cmpq	$(VEC_SIZE * 4), %rdx
 	jbe	L(last_4x_vec)
diff --git a/sysdeps/x86_64/multiarch/memrchr-evex.S b/sysdeps/x86_64/multiarch/memrchr-evex.S
index 3d3ef062e2..f7a11783c3 100644
--- a/sysdeps/x86_64/multiarch/memrchr-evex.S
+++ b/sysdeps/x86_64/multiarch/memrchr-evex.S
@@ -119,7 +119,7 @@ L(last_2x_vec):
 # endif
 	jle	L(zero_2)
 
-	/* We adjusted rax (length) for VEC_SIZE == 64 so need seperate
+	/* We adjusted rax (length) for VEC_SIZE == 64 so need separate
 	   offsets.  */
 # if VEC_SIZE == 64
 	vpcmpeqb (VEC_SIZE * -1)(%rdi, %rax), %VMATCH, %k0
@@ -354,7 +354,7 @@ L(loop_4x_vec):
 	jnz	L(first_vec_x1_end)
 	KMOV	%k2, %VRCX
 
-	/* Seperate logic for VEC_SIZE == 64 and VEC_SIZE == 32 for
+	/* Separate logic for VEC_SIZE == 64 and VEC_SIZE == 32 for
 	   returning last 2x VEC. For VEC_SIZE == 64 we test each VEC
 	   individually, for VEC_SIZE == 32 we combine them in a single
 	   64-bit GPR.  */
diff --git a/sysdeps/x86_64/multiarch/memrchr-sse2.S b/sysdeps/x86_64/multiarch/memrchr-sse2.S
index 8fdad16346..0ac707bc14 100644
--- a/sysdeps/x86_64/multiarch/memrchr-sse2.S
+++ b/sysdeps/x86_64/multiarch/memrchr-sse2.S
@@ -50,7 +50,7 @@ ENTRY_P2ALIGN(MEMRCHR, 6)
 	jz	L(page_cross)
 
 	/* NB: This load happens regardless of whether rdx (len) is zero. Since
-	   it doesn't cross a page and the standard gurantees any pointer have
+	   it doesn't cross a page and the standard guarantees any pointer have
 	   at least one-valid byte this load must be safe. For the entire
 	   history of the x86 memrchr implementation this has been possible so
 	   no code "should" be relying on a zero-length check before this load.
diff --git a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
index f37be6218a..3d9ad49cb9 100644
--- a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
+++ b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
@@ -199,7 +199,7 @@ L(less_vec_from_wmemset):
 	   MEMSET_VDUP_TO_VEC0_AND_SET_RETURN as ptr from here on out.  */
 	andl	$(PAGE_SIZE - 1), %edi
 	/* Check if VEC_SIZE store cross page. Mask stores suffer
-	   serious performance degradation when it has to fault supress.
+	   serious performance degradation when it has to fault suppress.
 	 */
 	cmpl	$(PAGE_SIZE - VEC_SIZE), %edi
 	/* This is generally considered a cold target.  */
diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S
index 52e6b186c8..0175a5e98c 100644<