convert to go buildpack

6 files changed, 3897 insertions, 0 deletions

diff --git a/vendor/github.com/google/gops/internal/obj/mips/a.out.go b/vendor/github.com/google/gops/internal/obj/mips/a.out.go
new file mode 100644
index 0000000..e0e51ee
--- /dev/null
+++ b/vendor/github.com/google/gops/internal/obj/mips/a.out.go
@@ -0,0 +1,375 @@
+// cmd/9c/9.out.h from Vita Nuova.
+//
+//	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
+//	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
+//	Portions Copyright © 1997-1999 Vita Nuova Limited
+//	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
+//	Portions Copyright © 2004,2006 Bruce Ellis
+//	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
+//	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
+//	Portions Copyright © 2009 The Go Authors. All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+
+package mips
+
+import "github.com/google/gops/internal/obj"
+
+//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p mips
+
+/*
+ * mips 64
+ */
+const (
+	NSNAME = 8
+	NSYM   = 50
+	NREG   = 32 /* number of general registers */
+	NFREG  = 32 /* number of floating point registers */
+)
+
+const (
+	REG_R0 = obj.RBaseMIPS64 + iota
+	REG_R1
+	REG_R2
+	REG_R3
+	REG_R4
+	REG_R5
+	REG_R6
+	REG_R7
+	REG_R8
+	REG_R9
+	REG_R10
+	REG_R11
+	REG_R12
+	REG_R13
+	REG_R14
+	REG_R15
+	REG_R16
+	REG_R17
+	REG_R18
+	REG_R19
+	REG_R20
+	REG_R21
+	REG_R22
+	REG_R23
+	REG_R24
+	REG_R25
+	REG_R26
+	REG_R27
+	REG_R28
+	REG_R29
+	REG_R30
+	REG_R31
+
+	REG_F0
+	REG_F1
+	REG_F2
+	REG_F3
+	REG_F4
+	REG_F5
+	REG_F6
+	REG_F7
+	REG_F8
+	REG_F9
+	REG_F10
+	REG_F11
+	REG_F12
+	REG_F13
+	REG_F14
+	REG_F15
+	REG_F16
+	REG_F17
+	REG_F18
+	REG_F19
+	REG_F20
+	REG_F21
+	REG_F22
+	REG_F23
+	REG_F24
+	REG_F25
+	REG_F26
+	REG_F27
+	REG_F28
+	REG_F29
+	REG_F30
+	REG_F31
+
+	REG_HI
+	REG_LO
+
+	// co-processor 0 control registers
+	REG_M0
+	REG_M1
+	REG_M2
+	REG_M3
+	REG_M4
+	REG_M5
+	REG_M6
+	REG_M7
+	REG_M8
+	REG_M9
+	REG_M10
+	REG_M11
+	REG_M12
+	REG_M13
+	REG_M14
+	REG_M15
+	REG_M16
+	REG_M17
+	REG_M18
+	REG_M19
+	REG_M20
+	REG_M21
+	REG_M22
+	REG_M23
+	REG_M24
+	REG_M25
+	REG_M26
+	REG_M27
+	REG_M28
+	REG_M29
+	REG_M30
+	REG_M31
+
+	// FPU control registers
+	REG_FCR0
+	REG_FCR1
+	REG_FCR2
+	REG_FCR3
+	REG_FCR4
+	REG_FCR5
+	REG_FCR6
+	REG_FCR7
+	REG_FCR8
+	REG_FCR9
+	REG_FCR10
+	REG_FCR11
+	REG_FCR12
+	REG_FCR13
+	REG_FCR14
+	REG_FCR15
+	REG_FCR16
+	REG_FCR17
+	REG_FCR18
+	REG_FCR19
+	REG_FCR20
+	REG_FCR21
+	REG_FCR22
+	REG_FCR23
+	REG_FCR24
+	REG_FCR25
+	REG_FCR26
+	REG_FCR27
+	REG_FCR28
+	REG_FCR29
+	REG_FCR30
+	REG_FCR31
+
+	REG_LAST = REG_FCR31 // the last defined register
+
+	REG_SPECIAL = REG_M0
+
+	REGZERO = REG_R0 /* set to zero */
+	REGSP   = REG_R29
+	REGSB   = REG_R28
+	REGLINK = REG_R31
+	REGRET  = REG_R1
+	REGARG  = -1      /* -1 disables passing the first argument in register */
+	REGRT1  = REG_R1  /* reserved for runtime, duffzero and duffcopy */
+	REGRT2  = REG_R2  /* reserved for runtime, duffcopy */
+	REGCTXT = REG_R22 /* context for closures */
+	REGG    = REG_R30 /* G */
+	REGTMP  = REG_R23 /* used by the linker */
+	FREGRET = REG_F0
+)
+
+const (
+	BIG = 32766
+)
+
+const (
+	/* mark flags */
+	FOLL    = 1 << 0
+	LABEL   = 1 << 1
+	LEAF    = 1 << 2
+	SYNC    = 1 << 3
+	BRANCH  = 1 << 4
+	LOAD    = 1 << 5
+	FCMP    = 1 << 6
+	NOSCHED = 1 << 7
+
+	NSCHED = 20
+)
+
+const (
+	C_NONE = iota
+	C_REG
+	C_FREG
+	C_FCREG
+	C_MREG /* special processor register */
+	C_HI
+	C_LO
+	C_ZCON
+	C_SCON /* 16 bit signed */
+	C_UCON /* 32 bit signed, low 16 bits 0 */
+	C_ADD0CON
+	C_AND0CON
+	C_ADDCON /* -0x8000 <= v < 0 */
+	C_ANDCON /* 0 < v <= 0xFFFF */
+	C_LCON   /* other 32 */
+	C_DCON   /* other 64 (could subdivide further) */
+	C_SACON  /* $n(REG) where n <= int16 */
+	C_SECON
+	C_LACON /* $n(REG) where int16 < n <= int32 */
+	C_LECON
+	C_DACON /* $n(REG) where int32 < n */
+	C_STCON /* $tlsvar */
+	C_SBRA
+	C_LBRA
+	C_SAUTO
+	C_LAUTO
+	C_SEXT
+	C_LEXT
+	C_ZOREG
+	C_SOREG
+	C_LOREG
+	C_GOK
+	C_ADDR
+	C_TLS
+	C_TEXTSIZE
+
+	C_NCLASS /* must be the last */
+)
+
+const (
+	AABSD = obj.ABaseMIPS64 + obj.A_ARCHSPECIFIC + iota
+	AABSF
+	AABSW
+	AADD
+	AADDD
+	AADDF
+	AADDU
+	AADDW
+	AAND
+	ABEQ
+	ABFPF
+	ABFPT
+	ABGEZ
+	ABGEZAL
+	ABGTZ
+	ABLEZ
+	ABLTZ
+	ABLTZAL
+	ABNE
+	ABREAK
+	ACMPEQD
+	ACMPEQF
+	ACMPGED
+	ACMPGEF
+	ACMPGTD
+	ACMPGTF
+	ADIV
+	ADIVD
+	ADIVF
+	ADIVU
+	ADIVW
+	AGOK
+	ALUI
+	AMOVB
+	AMOVBU
+	AMOVD
+	AMOVDF
+	AMOVDW
+	AMOVF
+	AMOVFD
+	AMOVFW
+	AMOVH
+	AMOVHU
+	AMOVW
+	AMOVWD
+	AMOVWF
+	AMOVWL
+	AMOVWR
+	AMUL
+	AMULD
+	AMULF
+	AMULU
+	AMULW
+	ANEGD
+	ANEGF
+	ANEGW
+	ANOR
+	AOR
+	AREM
+	AREMU
+	ARFE
+	ASGT
+	ASGTU
+	ASLL
+	ASRA
+	ASRL
+	ASUB
+	ASUBD
+	ASUBF
+	ASUBU
+	ASUBW
+	ASYSCALL
+	ATLBP
+	ATLBR
+	ATLBWI
+	ATLBWR
+	AWORD
+	AXOR
+
+	/* 64-bit */
+	AMOVV
+	AMOVVL
+	AMOVVR
+	ASLLV
+	ASRAV
+	ASRLV
+	ADIVV
+	ADIVVU
+	AREMV
+	AREMVU
+	AMULV
+	AMULVU
+	AADDV
+	AADDVU
+	ASUBV
+	ASUBVU
+
+	/* 64-bit FP */
+	ATRUNCFV
+	ATRUNCDV
+	ATRUNCFW
+	ATRUNCDW
+	AMOVWU
+	AMOVFV
+	AMOVDV
+	AMOVVF
+	AMOVVD
+
+	ALAST
+
+	// aliases
+	AJMP = obj.AJMP
+	AJAL = obj.ACALL
+	ARET = obj.ARET
+)
diff --git a/vendor/github.com/google/gops/internal/obj/mips/anames.go b/vendor/github.com/google/gops/internal/obj/mips/anames.go
new file mode 100644
index 0000000..06a366f
--- /dev/null
+++ b/vendor/github.com/google/gops/internal/obj/mips/anames.go
@@ -0,0 +1,113 @@
+// Generated by stringer -i a.out.go -o anames.go -p mips
+// Do not edit.
+
+package mips
+
+import "github.com/google/gops/internal/obj"
+
+var Anames = []string{
+	obj.A_ARCHSPECIFIC: "ABSD",
+	"ABSF",
+	"ABSW",
+	"ADD",
+	"ADDD",
+	"ADDF",
+	"ADDU",
+	"ADDW",
+	"AND",
+	"BEQ",
+	"BFPF",
+	"BFPT",
+	"BGEZ",
+	"BGEZAL",
+	"BGTZ",
+	"BLEZ",
+	"BLTZ",
+	"BLTZAL",
+	"BNE",
+	"BREAK",
+	"CMPEQD",
+	"CMPEQF",
+	"CMPGED",
+	"CMPGEF",
+	"CMPGTD",
+	"CMPGTF",
+	"DIV",
+	"DIVD",
+	"DIVF",
+	"DIVU",
+	"DIVW",
+	"GOK",
+	"LUI",
+	"MOVB",
+	"MOVBU",
+	"MOVD",
+	"MOVDF",
+	"MOVDW",
+	"MOVF",
+	"MOVFD",
+	"MOVFW",
+	"MOVH",
+	"MOVHU",
+	"MOVW",
+	"MOVWD",
+	"MOVWF",
+	"MOVWL",
+	"MOVWR",
+	"MUL",
+	"MULD",
+	"MULF",
+	"MULU",
+	"MULW",
+	"NEGD",
+	"NEGF",
+	"NEGW",
+	"NOR",
+	"OR",
+	"REM",
+	"REMU",
+	"RFE",
+	"SGT",
+	"SGTU",
+	"SLL",
+	"SRA",
+	"SRL",
+	"SUB",
+	"SUBD",
+	"SUBF",
+	"SUBU",
+	"SUBW",
+	"SYSCALL",
+	"TLBP",
+	"TLBR",
+	"TLBWI",
+	"TLBWR",
+	"WORD",
+	"XOR",
+	"MOVV",
+	"MOVVL",
+	"MOVVR",
+	"SLLV",
+	"SRAV",
+	"SRLV",
+	"DIVV",
+	"DIVVU",
+	"REMV",
+	"REMVU",
+	"MULV",
+	"MULVU",
+	"ADDV",
+	"ADDVU",
+	"SUBV",
+	"SUBVU",
+	"TRUNCFV",
+	"TRUNCDV",
+	"TRUNCFW",
+	"TRUNCDW",
+	"MOVWU",
+	"MOVFV",
+	"MOVDV",
+	"MOVVF",
+	"MOVVD",
+	"LAST",
+}
diff --git a/vendor/github.com/google/gops/internal/obj/mips/anames0.go b/vendor/github.com/google/gops/internal/obj/mips/anames0.go
new file mode 100644
index 0000000..c56d34e
--- /dev/null
+++ b/vendor/github.com/google/gops/internal/obj/mips/anames0.go
@@ -0,0 +1,44 @@
+// Copyright 2015 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package mips
+
+var cnames0 = []string{
+	"NONE",
+	"REG",
+	"FREG",
+	"FCREG",
+	"MREG",
+	"HI",
+	"LO",
+	"ZCON",
+	"SCON",
+	"UCON",
+	"ADD0CON",
+	"AND0CON",
+	"ADDCON",
+	"ANDCON",
+	"LCON",
+	"DCON",
+	"SACON",
+	"SECON",
+	"LACON",
+	"LECON",
+	"DACON",
+	"STCON",
+	"SBRA",
+	"LBRA",
+	"SAUTO",
+	"LAUTO",
+	"SEXT",
+	"LEXT",
+	"ZOREG",
+	"SOREG",
+	"LOREG",
+	"GOK",
+	"ADDR",
+	"TLS",
+	"TEXTSIZE",
+	"NCLASS",
+}
diff --git a/vendor/github.com/google/gops/internal/obj/mips/asm0.go b/vendor/github.com/google/gops/internal/obj/mips/asm0.go
new file mode 100644
index 0000000..ef4cedd
--- /dev/null
+++ b/vendor/github.com/google/gops/internal/obj/mips/asm0.go
@@ -0,0 +1,1783 @@
+// cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova.
+//
+//	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
+//	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
+//	Portions Copyright © 1997-1999 Vita Nuova Limited
+//	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
+//	Portions Copyright © 2004,2006 Bruce Ellis
+//	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
+//	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
+//	Portions Copyright © 2009 The Go Authors. All rights reserved.
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+
+package mips
+
+import (
+	"fmt"
+	"log"
+	"sort"
+
+	"github.com/google/gops/internal/obj"
+)
+
+// Instruction layout.
+
+const (
+	funcAlign = 8
+)
+
+const (
+	r0iszero = 1
+)
+
+type Optab struct {
+	as    obj.As
+	a1    uint8
+	a2    uint8
+	a3    uint8
+	type_ int8
+	size  int8
+	param int16
+}
+
+var optab = []Optab{
+	{obj.ATEXT, C_LEXT, C_NONE, C_TEXTSIZE, 0, 0, 0},
+	{obj.ATEXT, C_ADDR, C_NONE, C_TEXTSIZE, 0, 0, 0},
+
+	{AMOVW, C_REG, C_NONE, C_REG, 1, 4, 0},
+	{AMOVV, C_REG, C_NONE, C_REG, 1, 4, 0},
+	{AMOVB, C_REG, C_NONE, C_REG, 12, 8, 0},
+	{AMOVBU, C_REG, C_NONE, C_REG, 13, 4, 0},
+	{AMOVWU, C_REG, C_NONE, C_REG, 14, 8, 0},
+
+	{ASUB, C_REG, C_REG, C_REG, 2, 4, 0},
+	{AADD, C_REG, C_REG, C_REG, 2, 4, 0},
+	{AAND, C_REG, C_REG, C_REG, 2, 4, 0},
+	{ASUB, C_REG, C_NONE, C_REG, 2, 4, 0},
+	{AADD, C_REG, C_NONE, C_REG, 2, 4, 0},
+	{AAND, C_REG, C_NONE, C_REG, 2, 4, 0},
+
+	{ASLL, C_REG, C_NONE, C_REG, 9, 4, 0},
+	{ASLL, C_REG, C_REG, C_REG, 9, 4, 0},
+
+	{AADDF, C_FREG, C_NONE, C_FREG, 32, 4, 0},
+	{AADDF, C_FREG, C_REG, C_FREG, 32, 4, 0},
+	{ACMPEQF, C_FREG, C_REG, C_NONE, 32, 4, 0},
+	{AABSF, C_FREG, C_NONE, C_FREG, 33, 4, 0},
+	{AMOVF, C_FREG, C_NONE, C_FREG, 33, 4, 0},
+	{AMOVD, C_FREG, C_NONE, C_FREG, 33, 4, 0},
+
+	{AMOVW, C_REG, C_NONE, C_SEXT, 7, 4, REGSB},
+	{AMOVWU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB},
+	{AMOVV, C_REG, C_NONE, C_SEXT, 7, 4, REGSB},
+	{AMOVB, C_REG, C_NONE, C_SEXT, 7, 4, REGSB},
+	{AMOVBU, C_REG, C_NONE, C_SEXT, 7, 4, REGSB},
+	{AMOVWL, C_REG, C_NONE, C_SEXT, 7, 4, REGSB},
+	{AMOVW, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP},
+	{AMOVWU, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP},
+	{AMOVV, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP},
+	{AMOVB, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP},
+	{AMOVBU, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP},
+	{AMOVWL, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP},
+	{AMOVW, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO},
+	{AMOVWU, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO},
+	{AMOVV, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO},
+	{AMOVB, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO},
+	{AMOVBU, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO},
+	{AMOVWL, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO},
+
+	{AMOVW, C_SEXT, C_NONE, C_REG, 8, 4, REGSB},
+	{AMOVWU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB},
+	{AMOVV, C_SEXT, C_NONE, C_REG, 8, 4, REGSB},
+	{AMOVB, C_SEXT, C_NONE, C_REG, 8, 4, REGSB},
+	{AMOVBU, C_SEXT, C_NONE, C_REG, 8, 4, REGSB},
+	{AMOVWL, C_SEXT, C_NONE, C_REG, 8, 4, REGSB},
+	{AMOVW, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP},
+	{AMOVWU, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP},
+	{AMOVV, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP},
+	{AMOVB, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP},
+	{AMOVBU, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP},
+	{AMOVWL, C_SAUTO, C_NONE, C_REG, 8, 4, REGSP},
+	{AMOVW, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO},
+	{AMOVWU, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO},
+	{AMOVV, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO},
+	{AMOVB, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO},
+	{AMOVBU, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO},
+	{AMOVWL, C_SOREG, C_NONE, C_REG, 8, 4, REGZERO},
+
+	{AMOVW, C_REG, C_NONE, C_LEXT, 35, 12, REGSB},
+	{AMOVWU, C_REG, C_NONE, C_LEXT, 35, 12, REGSB},
+	{AMOVV, C_REG, C_NONE, C_LEXT, 35, 12, REGSB},
+	{AMOVB, C_REG, C_NONE, C_LEXT, 35, 12, REGSB},
+	{AMOVBU, C_REG, C_NONE, C_LEXT, 35, 12, REGSB},
+	{AMOVW, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP},
+	{AMOVWU, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP},
+	{AMOVV, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP},
+	{AMOVB, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP},
+	{AMOVBU, C_REG, C_NONE, C_LAUTO, 35, 12, REGSP},
+	{AMOVW, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO},
+	{AMOVWU, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO},
+	{AMOVV, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO},
+	{AMOVB, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO},
+	{AMOVBU, C_REG, C_NONE, C_LOREG, 35, 12, REGZERO},
+	{AMOVW, C_REG, C_NONE, C_ADDR, 50, 12, 0},
+	{AMOVWU, C_REG, C_NONE, C_ADDR, 50, 12, 0},
+	{AMOVV, C_REG, C_NONE, C_ADDR, 50, 12, 0},
+	{AMOVB, C_REG, C_NONE, C_ADDR, 50, 12, 0},
+	{AMOVBU, C_REG, C_NONE, C_ADDR, 50, 12, 0},
+	{AMOVW, C_REG, C_NONE, C_TLS, 53, 8, 0},
+	{AMOVWU, C_REG, C_NONE, C_TLS, 53, 8, 0},
+	{AMOVV, C_REG, C_NONE, C_TLS, 53, 8, 0},
+	{AMOVB, C_REG, C_NONE, C_TLS, 53, 8, 0},
+	{AMOVBU, C_REG, C_NONE, C_TLS, 53, 8, 0},
+
+	{AMOVW, C_LEXT, C_NONE, C_REG, 36, 12, REGSB},
+	{AMOVWU, C_LEXT, C_NONE, C_REG, 36, 12, REGSB},
+	{AMOVV, C_LEXT, C_NONE, C_REG, 36, 12, REGSB},
+	{AMOVB, C_LEXT, C_NONE, C_REG, 36, 12, REGSB},
+	{AMOVBU, C_LEXT, C_NONE, C_REG, 36, 12, REGSB},
+	{AMOVW, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP},
+	{AMOVWU, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP},
+	{AMOVV, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP},
+	{AMOVB, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP},
+	{AMOVBU, C_LAUTO, C_NONE, C_REG, 36, 12, REGSP},
+	{AMOVW, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO},
+	{AMOVWU, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO},
+	{AMOVV, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO},
+	{AMOVB, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO},
+	{AMOVBU, C_LOREG, C_NONE, C_REG, 36, 12, REGZERO},
+	{AMOVW, C_ADDR, C_NONE, C_REG, 51, 12, 0},
+	{AMOVWU, C_ADDR, C_NONE, C_REG, 51, 12, 0},
+	{AMOVV, C_ADDR, C_NONE, C_REG, 51, 12, 0},
+	{AMOVB, C_ADDR, C_NONE, C_REG, 51, 12, 0},
+	{AMOVBU, C_ADDR, C_NONE, C_REG, 51, 12, 0},
+	{AMOVW, C_TLS, C_NONE, C_REG, 54, 8, 0},
+	{AMOVWU, C_TLS, C_NONE, C_REG, 54, 8, 0},
+	{AMOVV, C_TLS, C_NONE, C_REG, 54, 8, 0},
+	{AMOVB, C_TLS, C_NONE, C_REG, 54, 8, 0},
+	{AMOVBU, C_TLS, C_NONE, C_REG, 54, 8, 0},
+
+	{AMOVW, C_SECON, C_NONE, C_REG, 3, 4, REGSB},
+	{AMOVV, C_SECON, C_NONE, C_REG, 3, 4, REGSB},
+	{AMOVW, C_SACON, C_NONE, C_REG, 3, 4, REGSP},
+	{AMOVV, C_SACON, C_NONE, C_REG, 3, 4, REGSP},
+	{AMOVW, C_LECON, C_NONE, C_REG, 52, 12, REGSB},
+	{AMOVV, C_LECON, C_NONE, C_REG, 52, 12, REGSB},
+	{AMOVW, C_LACON, C_NONE, C_REG, 26, 12, REGSP},
+	{AMOVV, C_LACON, C_NONE, C_REG, 26, 12, REGSP},
+	{AMOVW, C_ADDCON, C_NONE, C_REG, 3, 4, REGZERO},
+	{AMOVV, C_ADDCON, C_NONE, C_REG, 3, 4, REGZERO},
+	{AMOVW, C_ANDCON, C_NONE, C_REG, 3, 4, REGZERO},
+	{AMOVV, C_ANDCON, C_NONE, C_REG, 3, 4, REGZERO},
+	{AMOVW, C_STCON, C_NONE, C_REG, 55, 8, 0},
+	{AMOVV, C_STCON, C_NONE, C_REG, 55, 8, 0},
+
+	{AMOVW, C_UCON, C_NONE, C_REG, 24, 4, 0},
+	{AMOVV, C_UCON, C_NONE, C_REG, 24, 4, 0},
+	{AMOVW, C_LCON, C_NONE, C_REG, 19, 8, 0},
+	{AMOVV, C_LCON, C_NONE, C_REG, 19, 8, 0},
+
+	{AMOVW, C_HI, C_NONE, C_REG, 20, 4, 0},
+	{AMOVV, C_HI, C_NONE, C_REG, 20, 4, 0},
+	{AMOVW, C_LO, C_NONE, C_REG, 20, 4, 0},
+	{AMOVV, C_LO, C_NONE, C_REG, 20, 4, 0},
+	{AMOVW, C_REG, C_NONE, C_HI, 21, 4, 0},
+	{AMOVV, C_REG, C_NONE, C_HI, 21, 4, 0},
+	{AMOVW, C_REG, C_NONE, C_LO, 21, 4, 0},
+	{AMOVV, C_REG, C_NONE, C_LO, 21, 4, 0},
+
+	{AMUL, C_REG, C_REG, C_NONE, 22, 4, 0},
+
+	{AADD, C_ADD0CON, C_REG, C_REG, 4, 4, 0},
+	{AADD, C_ADD0CON, C_NONE, C_REG, 4, 4, 0},
+	{AADD, C_ANDCON, C_REG, C_REG, 10, 8, 0},
+	{AADD, C_ANDCON, C_NONE, C_REG, 10, 8, 0},
+
+	{AAND, C_AND0CON, C_REG, C_REG, 4, 4, 0},
+	{AAND, C_AND0CON, C_NONE, C_REG, 4, 4, 0},
+	{AAND, C_ADDCON, C_REG, C_REG, 10, 8, 0},
+	{AAND, C_ADDCON, C_NONE, C_REG, 10, 8, 0},
+
+	{AADD, C_UCON, C_REG, C_REG, 25, 8, 0},
+	{AADD, C_UCON, C_NONE, C_REG, 25, 8, 0},
+	{AAND, C_UCON, C_REG, C_REG, 25, 8, 0},
+	{AAND, C_UCON, C_NONE, C_REG, 25, 8, 0},
+
+	{AADD, C_LCON, C_NONE, C_REG, 23, 12, 0},
+	{AAND, C_LCON, C_NONE, C_REG, 23, 12, 0},
+	{AADD, C_LCON, C_REG, C_REG, 23, 12, 0},
+	{AAND, C_LCON, C_REG, C_REG, 23, 12, 0},
+
+	{ASLL, C_SCON, C_REG, C_REG, 16, 4, 0},
+	{ASLL, C_SCON, C_NONE, C_REG, 16, 4, 0},
+
+	{ASYSCALL, C_NONE, C_NONE, C_NONE, 5, 4, 0},
+
+	{ABEQ, C_REG, C_REG, C_SBRA, 6, 4, 0},
+	{ABEQ, C_REG, C_NONE, C_SBRA, 6, 4, 0},
+	{ABLEZ, C_REG, C_NONE, C_SBRA, 6, 4, 0},
+	{ABFPT, C_NONE, C_NONE, C_SBRA, 6, 8, 0},
+
+	{AJMP, C_NONE, C_NONE, C_LBRA, 11, 4, 0},
+	{AJAL, C_NONE, C_NONE, C_LBRA, 11, 4, 0},
+
+	{AJMP, C_NONE, C_NONE, C_ZOREG, 18, 4, REGZERO},
+	{AJAL, C_NONE, C_NONE, C_ZOREG, 18, 4, REGLINK},
+
+	{AMOVW, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB},
+	{AMOVF, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB},
+	{AMOVD, C_SEXT, C_NONE, C_FREG, 27, 4, REGSB},
+	{AMOVW, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP},
+	{AMOVF, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP},
+	{AMOVD, C_SAUTO, C_NONE, C_FREG, 27, 4, REGSP},
+	{AMOVW, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO},
+	{AMOVF, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO},
+	{AMOVD, C_SOREG, C_NONE, C_FREG, 27, 4, REGZERO},
+
+	{AMOVW, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB},
+	{AMOVF, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB},
+	{AMOVD, C_LEXT, C_NONE, C_FREG, 27, 12, REGSB},
+	{AMOVW, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP},
+	{AMOVF, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP},
+	{AMOVD, C_LAUTO, C_NONE, C_FREG, 27, 12, REGSP},
+	{AMOVW, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO},
+	{AMOVF, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO},
+	{AMOVD, C_LOREG, C_NONE, C_FREG, 27, 12, REGZERO},
+	{AMOVF, C_ADDR, C_NONE, C_FREG, 51, 12, 0},
+	{AMOVD, C_ADDR, C_NONE, C_FREG, 51, 12, 0},
+
+	{AMOVW, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB},
+	{AMOVF, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB},
+	{AMOVD, C_FREG, C_NONE, C_SEXT, 28, 4, REGSB},
+	{AMOVW, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP},
+	{AMOVF, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP},
+	{AMOVD, C_FREG, C_NONE, C_SAUTO, 28, 4, REGSP},
+	{AMOVW, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO},
+	{AMOVF, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO},
+	{AMOVD, C_FREG, C_NONE, C_SOREG, 28, 4, REGZERO},
+
+	{AMOVW, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB},
+	{AMOVF, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB},
+	{AMOVD, C_FREG, C_NONE, C_LEXT, 28, 12, REGSB},
+	{AMOVW, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP},
+	{AMOVF, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP},
+	{AMOVD, C_FREG, C_NONE, C_LAUTO, 28, 12, REGSP},
+	{AMOVW, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO},
+	{AMOVF, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO},
+	{AMOVD, C_FREG, C_NONE, C_LOREG, 28, 12, REGZERO},
+	{AMOVF, C_FREG, C_NONE, C_ADDR, 50, 12, 0},
+	{AMOVD, C_FREG, C_NONE, C_ADDR, 50, 12, 0},
+
+	{AMOVW, C_REG, C_NONE, C_FREG, 30, 4, 0},
+	{AMOVW, C_FREG, C_NONE, C_REG, 31, 4, 0},
+	{AMOVV, C_REG, C_NONE, C_FREG, 47, 4, 0},
+	{AMOVV, C_FREG, C_NONE, C_REG, 48, 4, 0},
+
+	{AMOVW, C_ADDCON, C_NONE, C_FREG, 34, 8, 0},
+	{AMOVW, C_ANDCON, C_NONE, C_FREG, 34, 8, 0},
+
+	{AMOVW, C_REG, C_NONE, C_MREG, 37, 4, 0},
+	{AMOVV, C_REG, C_NONE, C_MREG, 37, 4, 0},
+	{AMOVW, C_MREG, C_NONE, C_REG, 38, 4, 0},
+	{AMOVV, C_MREG, C_NONE, C_REG, 38, 4, 0},
+
+	{AWORD, C_LCON, C_NONE, C_NONE, 40, 4, 0},
+
+	{AMOVW, C_REG, C_NONE, C_FCREG, 41, 8, 0},
+	{AMOVV, C_REG, C_NONE, C_FCREG, 41, 8, 0},
+	{AMOVW, C_FCREG, C_NONE, C_REG, 42, 4, 0},
+	{AMOVV, C_FCREG, C_NONE, C_REG, 42, 4, 0},
+
+	{ABREAK, C_REG, C_NONE, C_SEXT, 7, 4, REGSB}, /* really CACHE instruction */
+	{ABREAK, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP},
+	{ABREAK, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO},
+	{ABREAK, C_NONE, C_NONE, C_NONE, 5, 4, 0},
+
+	{obj.AUNDEF, C_NONE, C_NONE, C_NONE, 49, 4, 0},
+	{obj.AUSEFIELD, C_ADDR, C_NONE, C_NONE, 0, 0, 0},
+	{obj.APCDATA, C_LCON, C_NONE, C_LCON, 0, 0, 0},
+	{obj.AFUNCDATA, C_SCON, C_NONE, C_ADDR, 0, 0, 0},
+	{obj.ANOP, C_NONE, C_NONE, C_NONE, 0, 0, 0},
+	{obj.ADUFFZERO, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as AJMP
+	{obj.ADUFFCOPY, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as AJMP
+
+	{obj.AXXX, C_NONE, C_NONE, C_NONE, 0, 4, 0},
+}
+
+var oprange [ALAST & obj.AMask][]Optab
+
+var xcmp [C_NCLASS][C_NCLASS]bool
+
+func span0(ctxt *obj.Link, cursym *obj.LSym) {
+	p := cursym.Text
+	if p == nil || p.Link == nil { // handle external functions and ELF section symbols
+		return
+	}
+	ctxt.Cursym = cursym
+	ctxt.Autosize = int32(p.To.Offset + 8)
+
+	if oprange[AOR&obj.AMask] == nil {
+		buildop(ctxt)
+	}
+
+	c := int64(0)
+	p.Pc = c
+
+	var m int
+	var o *Optab
+	for p = p.Link; p != nil; p = p.Link {
+		ctxt.Curp = p
+		p.Pc = c
+		o = oplook(ctxt, p)
+		m = int(o.size)
+		if m == 0 {
+			if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA && p.As != obj.AUSEFIELD {
+				ctxt.Diag("zero-width instruction\n%v", p)
+			}
+			continue
+		}
+
+		c += int64(m)
+	}
+
+	cursym.Size = c
+
+	/*
+	 * if any procedure is large enough to
+	 * generate a large SBRA branch, then
+	 * generate extra passes putting branches
+	 * around jmps to fix. this is rare.
+	 */
+	bflag := 1
+
+	var otxt int64
+	var q *obj.Prog
+	for bflag != 0 {
+		if ctxt.Debugvlog != 0 {
+			ctxt.Logf("%5.2f span1\n", obj.Cputime())
+		}
+		bflag = 0
+		c = 0
+		for p = cursym.Text.Link; p != nil; p = p.Link {
+			p.Pc = c
+			o = oplook(ctxt, p)
+
+			// very large conditional branches
+			if o.type_ == 6 && p.Pcond != nil {
+				otxt = p.Pcond.Pc - c
+				if otxt < -(1<<17)+10 || otxt >= (1<<17)-10 {
+					q = ctxt.NewProg()
+					q.Link = p.Link
+					p.Link = q
+					q.As = AJMP
+					q.Lineno = p.Lineno
+					q.To.Type = obj.TYPE_BRANCH
+					q.Pcond = p.Pcond
+					p.Pcond = q
+					q = ctxt.NewProg()
+					q.Link = p.Link
+					p.Link = q
+					q.As = AJMP
+					q.Lineno = p.Lineno
+					q.To.Type = obj.TYPE_BRANCH
+					q.Pcond = q.Link.Link
+
+					addnop(ctxt, p.Link)
+					addnop(ctxt, p)
+					bflag = 1
+				}
+			}
+
+			m = int(o.size)
+			if m == 0 {
+				if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA && p.As != obj.AUSEFIELD {
+					ctxt.Diag("zero-width instruction\n%v", p)
+				}
+				continue
+			}
+
+			c += int64(m)
+		}
+
+		cursym.Size = c
+	}
+
+	c += -c & (funcAlign - 1)
+	cursym.Size = c
+
+	/*
+	 * lay out the code, emitting code and data relocations.
+	 */
+
+	cursym.Grow(cursym.Size)
+
+	bp := cursym.P
+	var i int32
+	var out [4]uint32
+	for p := cursym.Text.Link; p != nil; p = p.Link {
+		ctxt.Pc = p.Pc
+		ctxt.Curp = p
+		o = oplook(ctxt, p)
+		if int(o.size) > 4*len(out) {
+			log.Fatalf("out array in span0 is too small, need at least %d for %v", o.size/4, p)
+		}
+		asmout(ctxt, p, o, out[:])
+		for i = 0; i < int32(o.size/4); i++ {
+			ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
+			bp = bp[4:]
+		}
+	}
+}
+
+func isint32(v int64) bool {
+	return int64(int32(v)) == v
+}
+
+func isuint32(v uint64) bool {
+	return uint64(uint32(v)) == v
+}
+
+func aclass(ctxt *obj.Link, a *obj.Addr) int {
+	switch a.Type {
+	case obj.TYPE_NONE:
+		return C_NONE
+
+	case obj.TYPE_REG:
+		if REG_R0 <= a.Reg && a.Reg <= REG_R31 {
+			return C_REG
+		}
+		if REG_F0 <= a.Reg && a.Reg <= REG_F31 {
+			return C_FREG
+		}
+		if REG_M0 <= a.Reg && a.Reg <= REG_M31 {
+			return C_MREG
+		}
+		if REG_FCR0 <= a.Reg && a.Reg <= REG_FCR31 {
+			return C_FCREG
+		}
+		if a.Reg == REG_LO {
+			return C_LO
+		}
+		if a.Reg == REG_HI {
+			return C_HI
+		}
+		return C_GOK
+
+	case obj.TYPE_MEM:
+		switch a.Name {
+		case obj.NAME_EXTERN,
+			obj.NAME_STATIC:
+			if a.Sym == nil {
+				break
+			}
+			ctxt.Instoffset = a.Offset
+			if a.Sym != nil { // use relocation
+				if a.Sym.Type == obj.STLSBSS {
+					return C_TLS
+				}
+				return C_ADDR
+			}
+			return C_LEXT
+
+		case obj.NAME_AUTO:
+			ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset
+			if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
+				return C_SAUTO
+			}
+			return C_LAUTO
+
+		case obj.NAME_PARAM:
+			ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + 8
+			if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
+				return C_SAUTO
+			}
+			return C_LAUTO
+
+		case obj.NAME_NONE:
+			ctxt.Instoffset = a.Offset
+			if ctxt.Instoffset == 0 {
+				return C_ZOREG
+			}
+			if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
+				return C_SOREG
+			}
+			return C_LOREG
+		}
+
+		return C_GOK
+
+	case obj.TYPE_TEXTSIZE:
+		return C_TEXTSIZE
+
+	case obj.TYPE_CONST,
+		obj.TYPE_ADDR:
+		switch a.Name {
+		case obj.NAME_NONE:
+			ctxt.Instoffset = a.Offset
+			if a.Reg != 0 {
+				if -BIG <= ctxt.Instoffset && ctxt.Instoffset <= BIG {
+					return C_SACON
+				}
+				if isint32(ctxt.Instoffset) {
+					return C_LACON
+				}
+				return C_DACON
+			}
+
+			goto consize
+
+		case obj.NAME_EXTERN,
+			obj.NAME_STATIC:
+			s := a.Sym
+			if s == nil {
+				break
+			}
+			if s.Type == obj.SCONST {
+				ctxt.Instoffset = a.Offset
+				goto consize
+			}
+
+			ctxt.Instoffset = a.Offset
+			if s.Type == obj.STLSBSS {
+				return C_STCON // address of TLS variable
+			}
+			return C_LECON
+
+		case obj.NAME_AUTO:
+			ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset
+			if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
+				return C_SACON
+			}
+			return C_LACON
+
+		case obj.NAME_PARAM:
+			ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + 8
+			if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
+				return C_SACON
+			}
+			return C_LACON
+		}
+
+		return C_GOK
+
+	consize:
+		if ctxt.Instoffset >= 0 {
+			if ctxt.Instoffset == 0 {
+				return C_ZCON
+			}
+			if ctxt.Instoffset <= 0x7fff {
+				return C_SCON
+			}
+			if ctxt.Instoffset <= 0xffff {
+				return C_ANDCON
+			}
+			if ctxt.Instoffset&0xffff == 0 && isuint32(uint64(ctxt.Instoffset)) { /* && (instoffset & (1<<31)) == 0) */
+				return C_UCON
+			}
+			if isint32(ctxt.Instoffset) || isuint32(uint64(ctxt.Instoffset)) {
+				return C_LCON
+			}
+			return C_LCON // C_DCON
+		}
+
+		if ctxt.Instoffset >= -0x8000 {
+			return C_ADDCON
+		}
+		if ctxt.Instoffset&0xffff == 0 && isint32(ctxt.Instoffset) {
+			return C_UCON
+		}
+		if isint32(ctxt.Instoffset) {
+			return C_LCON
+		}
+		return C_LCON // C_DCON
+
+	case obj.TYPE