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authorSunil K Pandey <skpgkp2@gmail.com>2021-12-29 09:29:44 -0800
committerSunil K Pandey <skpgkp2@gmail.com>2021-12-29 11:38:21 -0800
commit7e1722fec84c65bf95f249f9ad8d15ab12d8c853 (patch)
tree6c0b107f2c3f2081a8ad639a9a298c30a5506501
parent8f8566026dbe4ab104cab5845c4cdc9896702fdb (diff)
downloadglibc-7e1722fec84c65bf95f249f9ad8d15ab12d8c853.tar.xz
glibc-7e1722fec84c65bf95f249f9ad8d15ab12d8c853.zip
x86-64: Add vector log2/log2f implementation to libmvec
Implement vectorized log2/log2f containing SSE, AVX, AVX2 and AVX512 versions for libmvec as per vector ABI. It also contains accuracy and ABI tests for vector log2/log2f with regenerated ulps. Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
-rw-r--r--bits/libm-simd-decl-stubs.h11
-rw-r--r--math/bits/mathcalls.h2
-rw-r--r--sysdeps/unix/sysv/linux/x86_64/libmvec.abilist8
-rw-r--r--sysdeps/x86/fpu/bits/math-vector.h4
-rw-r--r--sysdeps/x86/fpu/finclude/math-vector-fortran.h4
-rw-r--r--sysdeps/x86_64/fpu/Makeconfig1
-rw-r--r--sysdeps/x86_64/fpu/Versions2
-rw-r--r--sysdeps/x86_64/fpu/libm-test-ulps20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_log22_core-sse2.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_log22_core.c27
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_log22_core_sse4.S1339
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_log24_core-sse.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_log24_core.c27
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_log24_core_avx2.S1324
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_log28_core-avx2.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_log28_core.c27
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_d_log28_core_avx512.S293
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_log2f16_core-avx2.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_log2f16_core.c28
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_log2f16_core_avx512.S231
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_log2f4_core-sse2.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_log2f4_core.c28
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_log2f4_core_sse4.S223
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_log2f8_core-sse.S20
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_log2f8_core.c28
-rw-r--r--sysdeps/x86_64/fpu/multiarch/svml_s_log2f8_core_avx2.S226
-rw-r--r--sysdeps/x86_64/fpu/svml_d_log22_core.S29
-rw-r--r--sysdeps/x86_64/fpu/svml_d_log24_core.S29
-rw-r--r--sysdeps/x86_64/fpu/svml_d_log24_core_avx.S25
-rw-r--r--sysdeps/x86_64/fpu/svml_d_log28_core.S25
-rw-r--r--sysdeps/x86_64/fpu/svml_s_log2f16_core.S25
-rw-r--r--sysdeps/x86_64/fpu/svml_s_log2f4_core.S29
-rw-r--r--sysdeps/x86_64/fpu/svml_s_log2f8_core.S29
-rw-r--r--sysdeps/x86_64/fpu/svml_s_log2f8_core_avx.S25
-rw-r--r--sysdeps/x86_64/fpu/test-double-libmvec-log2-avx.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-libmvec-log2-avx2.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-libmvec-log2-avx512f.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-libmvec-log2.c3
-rw-r--r--sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-libmvec-log2f-avx.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-libmvec-log2f-avx2.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-libmvec-log2f-avx512f.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-libmvec-log2f.c3
-rw-r--r--sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c1
-rw-r--r--sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c1
50 files changed, 4208 insertions, 1 deletions
diff --git a/bits/libm-simd-decl-stubs.h b/bits/libm-simd-decl-stubs.h
index 4ad584c227..73252615ca 100644
--- a/bits/libm-simd-decl-stubs.h
+++ b/bits/libm-simd-decl-stubs.h
@@ -230,4 +230,15 @@
#define __DECL_SIMD_log10f32x
#define __DECL_SIMD_log10f64x
#define __DECL_SIMD_log10f128x
+
+#define __DECL_SIMD_log2
+#define __DECL_SIMD_log2f
+#define __DECL_SIMD_log2l
+#define __DECL_SIMD_log2f16
+#define __DECL_SIMD_log2f32
+#define __DECL_SIMD_log2f64
+#define __DECL_SIMD_log2f128
+#define __DECL_SIMD_log2f32x
+#define __DECL_SIMD_log2f64x
+#define __DECL_SIMD_log2f128x
#endif
diff --git a/math/bits/mathcalls.h b/math/bits/mathcalls.h
index f21384758a..bfe52a4666 100644
--- a/math/bits/mathcalls.h
+++ b/math/bits/mathcalls.h
@@ -130,7 +130,7 @@ __MATHCALL (logb,, (_Mdouble_ __x));
__MATHCALL_VEC (exp2,, (_Mdouble_ __x));
/* Compute base-2 logarithm of X. */
-__MATHCALL (log2,, (_Mdouble_ __x));
+__MATHCALL_VEC (log2,, (_Mdouble_ __x));
#endif
diff --git a/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist b/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist
index 8108a2a189..fa8b016c5d 100644
--- a/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist
@@ -55,6 +55,7 @@ GLIBC_2.35 _ZGVbN2v_exp10 F
GLIBC_2.35 _ZGVbN2v_exp2 F
GLIBC_2.35 _ZGVbN2v_expm1 F
GLIBC_2.35 _ZGVbN2v_log10 F
+GLIBC_2.35 _ZGVbN2v_log2 F
GLIBC_2.35 _ZGVbN2v_sinh F
GLIBC_2.35 _ZGVbN2vv_atan2 F
GLIBC_2.35 _ZGVbN2vv_hypot F
@@ -67,6 +68,7 @@ GLIBC_2.35 _ZGVbN4v_exp10f F
GLIBC_2.35 _ZGVbN4v_exp2f F
GLIBC_2.35 _ZGVbN4v_expm1f F
GLIBC_2.35 _ZGVbN4v_log10f F
+GLIBC_2.35 _ZGVbN4v_log2f F
GLIBC_2.35 _ZGVbN4v_sinhf F
GLIBC_2.35 _ZGVbN4vv_atan2f F
GLIBC_2.35 _ZGVbN4vv_hypotf F
@@ -79,6 +81,7 @@ GLIBC_2.35 _ZGVcN4v_exp10 F
GLIBC_2.35 _ZGVcN4v_exp2 F
GLIBC_2.35 _ZGVcN4v_expm1 F
GLIBC_2.35 _ZGVcN4v_log10 F
+GLIBC_2.35 _ZGVcN4v_log2 F
GLIBC_2.35 _ZGVcN4v_sinh F
GLIBC_2.35 _ZGVcN4vv_atan2 F
GLIBC_2.35 _ZGVcN4vv_hypot F
@@ -91,6 +94,7 @@ GLIBC_2.35 _ZGVcN8v_exp10f F
GLIBC_2.35 _ZGVcN8v_exp2f F
GLIBC_2.35 _ZGVcN8v_expm1f F
GLIBC_2.35 _ZGVcN8v_log10f F
+GLIBC_2.35 _ZGVcN8v_log2f F
GLIBC_2.35 _ZGVcN8v_sinhf F
GLIBC_2.35 _ZGVcN8vv_atan2f F
GLIBC_2.35 _ZGVcN8vv_hypotf F
@@ -103,6 +107,7 @@ GLIBC_2.35 _ZGVdN4v_exp10 F
GLIBC_2.35 _ZGVdN4v_exp2 F
GLIBC_2.35 _ZGVdN4v_expm1 F
GLIBC_2.35 _ZGVdN4v_log10 F
+GLIBC_2.35 _ZGVdN4v_log2 F
GLIBC_2.35 _ZGVdN4v_sinh F
GLIBC_2.35 _ZGVdN4vv_atan2 F
GLIBC_2.35 _ZGVdN4vv_hypot F
@@ -115,6 +120,7 @@ GLIBC_2.35 _ZGVdN8v_exp10f F
GLIBC_2.35 _ZGVdN8v_exp2f F
GLIBC_2.35 _ZGVdN8v_expm1f F
GLIBC_2.35 _ZGVdN8v_log10f F
+GLIBC_2.35 _ZGVdN8v_log2f F
GLIBC_2.35 _ZGVdN8v_sinhf F
GLIBC_2.35 _ZGVdN8vv_atan2f F
GLIBC_2.35 _ZGVdN8vv_hypotf F
@@ -127,6 +133,7 @@ GLIBC_2.35 _ZGVeN16v_exp10f F
GLIBC_2.35 _ZGVeN16v_exp2f F
GLIBC_2.35 _ZGVeN16v_expm1f F
GLIBC_2.35 _ZGVeN16v_log10f F
+GLIBC_2.35 _ZGVeN16v_log2f F
GLIBC_2.35 _ZGVeN16v_sinhf F
GLIBC_2.35 _ZGVeN16vv_atan2f F
GLIBC_2.35 _ZGVeN16vv_hypotf F
@@ -139,6 +146,7 @@ GLIBC_2.35 _ZGVeN8v_exp10 F
GLIBC_2.35 _ZGVeN8v_exp2 F
GLIBC_2.35 _ZGVeN8v_expm1 F
GLIBC_2.35 _ZGVeN8v_log10 F
+GLIBC_2.35 _ZGVeN8v_log2 F
GLIBC_2.35 _ZGVeN8v_sinh F
GLIBC_2.35 _ZGVeN8vv_atan2 F
GLIBC_2.35 _ZGVeN8vv_hypot F
diff --git a/sysdeps/x86/fpu/bits/math-vector.h b/sysdeps/x86/fpu/bits/math-vector.h
index 64e80ada7a..59d284a10a 100644
--- a/sysdeps/x86/fpu/bits/math-vector.h
+++ b/sysdeps/x86/fpu/bits/math-vector.h
@@ -106,6 +106,10 @@
# define __DECL_SIMD_log10 __DECL_SIMD_x86_64
# undef __DECL_SIMD_log10f
# define __DECL_SIMD_log10f __DECL_SIMD_x86_64
+# undef __DECL_SIMD_log2
+# define __DECL_SIMD_log2 __DECL_SIMD_x86_64
+# undef __DECL_SIMD_log2f
+# define __DECL_SIMD_log2f __DECL_SIMD_x86_64
# endif
#endif
diff --git a/sysdeps/x86/fpu/finclude/math-vector-fortran.h b/sysdeps/x86/fpu/finclude/math-vector-fortran.h
index f5050c68af..a2ca9a203f 100644
--- a/sysdeps/x86/fpu/finclude/math-vector-fortran.h
+++ b/sysdeps/x86/fpu/finclude/math-vector-fortran.h
@@ -52,6 +52,8 @@
!GCC$ builtin (atan2f) attributes simd (notinbranch) if('x86_64')
!GCC$ builtin (log10) attributes simd (notinbranch) if('x86_64')
!GCC$ builtin (log10f) attributes simd (notinbranch) if('x86_64')
+!GCC$ builtin (log2) attributes simd (notinbranch) if('x86_64')
+!GCC$ builtin (log2f) attributes simd (notinbranch) if('x86_64')
!GCC$ builtin (cos) attributes simd (notinbranch) if('x32')
!GCC$ builtin (cosf) attributes simd (notinbranch) if('x32')
@@ -89,3 +91,5 @@
!GCC$ builtin (atan2f) attributes simd (notinbranch) if('x32')
!GCC$ builtin (log10) attributes simd (notinbranch) if('x32')
!GCC$ builtin (log10f) attributes simd (notinbranch) if('x32')
+!GCC$ builtin (log2) attributes simd (notinbranch) if('x32')
+!GCC$ builtin (log2f) attributes simd (notinbranch) if('x32')
diff --git a/sysdeps/x86_64/fpu/Makeconfig b/sysdeps/x86_64/fpu/Makeconfig
index ba37044e9d..8d6d0915af 100644
--- a/sysdeps/x86_64/fpu/Makeconfig
+++ b/sysdeps/x86_64/fpu/Makeconfig
@@ -36,6 +36,7 @@ libmvec-funcs = \
hypot \
log \
log10 \
+ log2 \
pow \
sin \
sincos \
diff --git a/sysdeps/x86_64/fpu/Versions b/sysdeps/x86_64/fpu/Versions
index 8beaf0736f..1b48c2d642 100644
--- a/sysdeps/x86_64/fpu/Versions
+++ b/sysdeps/x86_64/fpu/Versions
@@ -23,6 +23,7 @@ libmvec {
_ZGVbN2v_exp2; _ZGVcN4v_exp2; _ZGVdN4v_exp2; _ZGVeN8v_exp2;
_ZGVbN2v_expm1; _ZGVcN4v_expm1; _ZGVdN4v_expm1; _ZGVeN8v_expm1;
_ZGVbN2v_log10; _ZGVcN4v_log10; _ZGVdN4v_log10; _ZGVeN8v_log10;
+ _ZGVbN2v_log2; _ZGVcN4v_log2; _ZGVdN4v_log2; _ZGVeN8v_log2;
_ZGVbN2v_sinh; _ZGVcN4v_sinh; _ZGVdN4v_sinh; _ZGVeN8v_sinh;
_ZGVbN2vv_atan2; _ZGVcN4vv_atan2; _ZGVdN4vv_atan2; _ZGVeN8vv_atan2;
_ZGVbN2vv_hypot; _ZGVcN4vv_hypot; _ZGVdN4vv_hypot; _ZGVeN8vv_hypot;
@@ -35,6 +36,7 @@ libmvec {
_ZGVbN4v_exp2f; _ZGVcN8v_exp2f; _ZGVdN8v_exp2f; _ZGVeN16v_exp2f;
_ZGVbN4v_expm1f; _ZGVcN8v_expm1f; _ZGVdN8v_expm1f; _ZGVeN16v_expm1f;
_ZGVbN4v_log10f; _ZGVcN8v_log10f; _ZGVdN8v_log10f; _ZGVeN16v_log10f;
+ _ZGVbN4v_log2f; _ZGVcN8v_log2f; _ZGVdN8v_log2f; _ZGVeN16v_log2f;
_ZGVbN4v_sinhf; _ZGVcN8v_sinhf; _ZGVdN8v_sinhf; _ZGVeN16v_sinhf;
_ZGVbN4vv_atan2f; _ZGVcN8vv_atan2f; _ZGVdN8vv_atan2f; _ZGVeN16vv_atan2f;
_ZGVbN4vv_hypotf; _ZGVcN8vv_hypotf; _ZGVdN8vv_hypotf; _ZGVeN16vv_hypotf;
diff --git a/sysdeps/x86_64/fpu/libm-test-ulps b/sysdeps/x86_64/fpu/libm-test-ulps
index b0cd9d60ea..3b7f3cee6f 100644
--- a/sysdeps/x86_64/fpu/libm-test-ulps
+++ b/sysdeps/x86_64/fpu/libm-test-ulps
@@ -1709,6 +1709,26 @@ float: 3
float128: 1
ldouble: 1
+Function: "log2_vlen16":
+float: 1
+
+Function: "log2_vlen2":
+double: 1
+
+Function: "log2_vlen4":
+double: 1
+float: 1
+
+Function: "log2_vlen4_avx2":
+double: 1
+
+Function: "log2_vlen8":
+double: 1
+float: 1
+
+Function: "log2_vlen8_avx2":
+float: 1
+
Function: "log_downward":
float: 2
float128: 1
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log22_core-sse2.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log22_core-sse2.S
new file mode 100644
index 0000000000..e0833a174b
--- /dev/null
+++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log22_core-sse2.S
@@ -0,0 +1,20 @@
+/* SSE2 version of vectorized log2, vector length is 2.
+ Copyright (C) 2021 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define _ZGVbN2v_log2 _ZGVbN2v_log2_sse2
+#include "../svml_d_log22_core.S"
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log22_core.c b/sysdeps/x86_64/fpu/multiarch/svml_d_log22_core.c
new file mode 100644
index 0000000000..6d0b5a03ca
--- /dev/null
+++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log22_core.c
@@ -0,0 +1,27 @@
+/* Multiple versions of vectorized log2, vector length is 2.
+ Copyright (C) 2021 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define SYMBOL_NAME _ZGVbN2v_log2
+#include "ifunc-mathvec-sse4_1.h"
+
+libc_ifunc_redirected (REDIRECT_NAME, SYMBOL_NAME, IFUNC_SELECTOR ());
+
+#ifdef SHARED
+__hidden_ver1 (_ZGVbN2v_log2, __GI__ZGVbN2v_log2, __redirect__ZGVbN2v_log2)
+ __attribute__ ((visibility ("hidden")));
+#endif
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log22_core_sse4.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log22_core_sse4.S
new file mode 100644
index 0000000000..51e67d845b
--- /dev/null
+++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log22_core_sse4.S</