| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2025-01-01 | Update copyright dates with scripts/update-copyrights | Paul Eggert | 1 | -1/+1 | |
| 2024-01-01 | Update copyright dates with scripts/update-copyrights | Paul Eggert | 1 | -1/+1 | |
| 2023-12-20 | aarch64: Add half-width versions of AdvSIMD f32 libmvec routines | Joe Ramsay | 1 | -1/+3 | |
| Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com> | |||||
| 2023-11-10 | aarch64: Add vector implementations of asin routines | Joe Ramsay | 1 | -0/+104 | |
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