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Age	Commit message (Collapse)	Author	Files	Lines
2025-01-01	Update copyright dates with scripts/update-copyrights	Paul Eggert	1	-1/+1

2024-12-09	AArch64: Improve codegen in AdvSIMD logs	Pierre Blanchard	1	-30/+43
	Remove spurious ADRP and a few MOVs. Reduce memory access by using more indexed MLAs in polynomial. Align notation so that algorithms are easier to compare. Speedup on Neoverse V1 for log10 (8%), log (8.5%), and log2 (10%). Update error threshold in AdvSIMD log (now matches SVE log).
2024-05-14	aarch64: Fix AdvSIMD libmvec routines for big-endian	Joe Ramsay	1	-2/+4
	Previously many routines used * to load from vector types stored in the data table. This is emitted as ldr, which byte-swaps the entire vector register, and causes bugs for big-endian when not all lanes contain the same value. When a vector is to be used this way, it has been replaced with an array and the load with an explicit ld1 intrinsic, which byte-swaps only within lanes. As well, many routines previously used non-standard GCC syntax for vector operations such as indexing into vectors types with [] and assembling vectors using {}. This syntax should not be mixed with ACLE, as the former does not respect endianness whereas the latter does. Such examples have been replaced with, for instance, vcombine_* and vgetq_lane* intrinsics. Helpers which only use the GCC syntax, such as the v_call helpers, do not need changing as they do not use intrinsics. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-01-01	Update copyright dates with scripts/update-copyrights	Paul Eggert	1	-1/+1

2023-10-23	aarch64: Add vector implementations of log2 routines	Joe Ramsay	1	-0/+109
	A table is also added, which is shared between AdvSIMD and SVE log2.