| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2025-01-01 | Update copyright dates with scripts/update-copyrights | Paul Eggert | 1 | -1/+1 | |
| 2024-01-01 | Update copyright dates with scripts/update-copyrights | Paul Eggert | 1 | -1/+1 | |
| 2023-10-05 | aarch64: Optimise vecmath logs | Joe Ramsay | 1 | -130/+130 | |
| * Transpose table layout for improved memory access * Use half-vector special comparisons for AdvSIMD * Improve register use near special-case branches - Due to the presence of a function call, return value would get mov-d out of x0 in order to facilitate PCS. By moving the final computation after the branch this can be avoided Also change SVE routines to use overloaded intrinsics for readability. | |||||
| 2023-06-30 | aarch64: Add vector implementations of log routines | Joe Ramsay | 1 | -0/+173 | |
| Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. Log lookup table added as HIDDEN symbol to allow it to be shared between AdvSIMD and SVE variants. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com> | |||||
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index : glibc.git | |
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