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2025-01-03AArch64: Add vector tanpi routinesJoe Ramsay1-0/+5
Vector variant of the new C23 tanpi. New tests pass on AArch64.
2025-01-03AArch64: Add vector cospi routinesJoe Ramsay1-0/+5
Vector variant of the new C23 cospi. New tests pass on AArch64.
2025-01-03AArch64: Add vector sinpi to libmvecJoe Ramsay1-0/+5
Vector variant of the new C23 sinpi. New tests pass on AArch64.
2024-09-19AArch64: Add vector logp1 alias for log1pJoe Ramsay1-0/+7
This enables vectorisation of C23 logp1, which is an alias for log1p. There are no new tests or ulp entries because the new symbols are simply aliases. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
2024-05-21aarch64/fpu: Add vector variants of powJoe Ramsay1-0/+5
Plus a small amount of moving includes around in order to be able to remove duplicate definition of asuint64. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-16aarch64/fpu: Add vector variants of cbrtJoe Ramsay1-0/+5
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-16aarch64/fpu: Add vector variants of hypotJoe Ramsay1-0/+5
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-04aarch64/fpu: Add vector variants of erfcJoe Ramsay1-0/+5
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-04aarch64/fpu: Add vector variants of tanhJoe Ramsay1-0/+5
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-04aarch64/fpu: Add vector variants of sinhJoe Ramsay1-0/+5
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-04aarch64/fpu: Add vector variants of atanhJoe Ramsay1-0/+5
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-04aarch64/fpu: Add vector variants of asinhJoe Ramsay1-0/+5
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-04aarch64/fpu: Add vector variants of acoshJoe Ramsay1-0/+5
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-04aarch64/fpu: Add vector variants of coshJoe Ramsay1-0/+5
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-04-04aarch64/fpu: Add vector variants of erfJoe Ramsay1-0/+7
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-12-20aarch64: Add half-width versions of AdvSIMD f32 libmvec routinesJoe Ramsay1-0/+15
Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-11-20aarch64: Add vector implementations of expm1 routinesJoe Ramsay1-0/+4
May discard sign of 0 - auto tests for -0 and -0x1p-10000 updated accordingly.
2023-11-10aarch64: Add vector implementations of log1p routinesJoe Ramsay1-0/+4
May discard sign of zero.
2023-11-10aarch64: Add vector implementations of atan2 routinesJoe Ramsay1-0/+4
2023-11-10aarch64: Add vector implementations of atan routinesJoe Ramsay1-0/+4
2023-11-10aarch64: Add vector implementations of acos routinesJoe Ramsay1-0/+4
2023-11-10aarch64: Add vector implementations of asin routinesJoe Ramsay1-0/+4
2023-10-23aarch64: Add vector implementations of exp10 routinesJoe Ramsay1-0/+4
Double-precision routines either reuse the exp table (AdvSIMD) or use SVE FEXPA intruction.
2023-10-23aarch64: Add vector implementations of log10 routinesJoe Ramsay1-0/+4
A table is also added, which is shared between AdvSIMD and SVE log10.
2023-10-23aarch64: Add vector implementations of log2 routinesJoe Ramsay1-0/+4
A table is also added, which is shared between AdvSIMD and SVE log2.
2023-10-23aarch64: Add vector implementations of exp2 routinesJoe Ramsay1-0/+4
Some routines reuse table from v_exp_data.c
2023-10-23aarch64: Add vector implementations of tan routinesJoe Ramsay1-0/+6
This includes some utility headers for evaluating polynomials using various schemes.
2023-06-30aarch64: Add vector implementations of exp routinesJoe Ramsay1-0/+4
Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-30aarch64: Add vector implementations of log routinesJoe Ramsay1-0/+4
Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. Log lookup table added as HIDDEN symbol to allow it to be shared between AdvSIMD and SVE variants. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-30aarch64: Add vector implementations of sin routinesJoe Ramsay1-0/+4
Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-05-03Enable libmvec support for AArch64Joe Ramsay1-0/+8
This patch enables libmvec on AArch64. The proposed change is mainly implementing build infrastructure to add the new routines to ABI, tests and benchmarks. I have demonstrated how this all fits together by adding implementations for vector cos, in both single and double precision, targeting both Advanced SIMD and SVE. The implementations of the routines themselves are just loops over the scalar routine from libm for now, as we are more concerned with getting the plumbing right at this point. We plan to contribute vector routines from the Arm Optimized Routines repo that are compliant with requirements described in the libmvec wiki. Building libmvec requires minimum GCC 10 for SVE ACLE. To avoid raising the minimum GCC by such a big jump, we allow users to disable libmvec if their compiler is too old. Note that at this point users have to manually call the vector math functions. This seems to be acceptable to some downstream users. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>